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1. (WO2018004941) METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING BY LAGRANGIAN POLYNOMIAL FITTING
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/004941 International Application No.: PCT/US2017/035118
Publication Date: 04.01.2018 International Filing Date: 31.05.2017
IPC:
H03M 13/15 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05
using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13
Linear codes
15
Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem (BCH) codes
Applicants:
ALTERA CORPORATION [US/US]; 101 Innovation Drive San Jose, CA 95134, US
Inventors:
LANGHAMMER, Martin; GB
FINN, Simon; GB
MUMTAZ, Sami; GB
Agent:
TSAI, Jason; US
Priority Data:
15/197,43329.06.2016US
Title (EN) METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING BY LAGRANGIAN POLYNOMIAL FITTING
(FR) PROCÉDÉ ET APPAREIL PERMETTANT D'EFFECTUER UN CODAGE DE REED-SOLOMON PAR AJUSTEMENT POLYNOMIALE DE LAGRANGE
Abstract:
(EN) An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute parity check symbols by multiplying the partial syndromes by predetermined Lagrangian polynomial coefficients. The parity check symbol generation step may be performed in one clock cycle or multiple clock cycles.
(FR) L'invention concerne un circuit intégré permettant de mettre en œuvre un circuit codeur de Reed-Solomon. Le circuit codeur peut comprendre une circuiterie de calcul de syndrome partiel et une circuiterie de multiplication de matrice. La circuiterie de calcul de syndrome partiel peut recevoir un message et générer des syndromes partiels correspondants. La circuiterie de multiplication de matrice peut recevoir les syndromes partiels et calculer des symboles de contrôle de parité en multipliant les syndromes partiels par des coefficients de polynôme de Lagrange prédéterminés. L'étape de génération de symboles de contrôle de parité peut être effectuée dans un ou plusieurs cycles d'horloge.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)