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1. (WO2018004907) INTEGRATED CIRCUIT PACKAGE STACK
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/004907 International Application No.: PCT/US2017/034761
Publication Date: 04.01.2018 International Filing Date: 26.05.2017
IPC:
H01L 25/07 (2006.01) ,H01L 25/065 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/538 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
JAYARAMAN, Saikumar; US
GUZEK, John S.; US
MEKONNEN, Yidnekachew S.; US
Agent:
MARLINK, Jeffrey S.; US
AUYEUNG, Al; US
BLAIR, Steven R.; US
COFIELD, Michael A.; US
COWGER, Graciela G.; US
DANSKIN, Timothy A.; US
FORD, Stephen S.; US
GARTHWAITE, Martin S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MEININGER, Mark M.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
15/196,93729.06.2016US
Title (EN) INTEGRATED CIRCUIT PACKAGE STACK
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ
Abstract:
(EN) Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
(FR) L'invention concerne également des appareils, des procédés et des systèmes associés à la conception du boîtier de circuit intégré (CI). Une pile de boîtiers de circuit intégré peut comprendre un premier boîtier de circuit intégré et un second boîtier de circuit intégré. Le premier boîtier de circuit intégré peut comprendre une première puce et une première couche de redistribution qui couple de manière communicative des contacts sur le premier côté du premier boîtier de circuit intégré à la première puce et à des contacts sur un second côté du premier boîtier de circuit intégré, le second côté étant opposé au premier côté. Le second boîtier de circuit intégré peut être monté sur le second côté du premier boîtier de circuit intégré. Le second boîtier de circuit intégré peut comprendre une seconde puce et une seconde couche de redistribution qui couple de manière communicative des contacts sur un côté du second boîtier de circuit intégré à la seconde puce, les contacts du second boîtier de circuit intégré étant couplés manière communicative aux contacts sur le second côté du premier boîtier de circuit intégré.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP3479403