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1. WO2018004807 - LATCH-BASED POWER-ON CHECKER

Publication Number WO/2018/004807
Publication Date 04.01.2018
International Application No. PCT/US2017/029471
International Filing Date 25.04.2017
Chapter 2 Demand Filed 01.09.2017
IPC
H03K 17/22 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and -breaking
22Modifications for ensuring a predetermined initial state when the supply voltage has been applied
G06F 1/24 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
24Resetting means
CPC
G06F 1/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
H03K 17/223
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and –breaking
22Modifications for ensuring a predetermined initial state when the supply voltage has been applied
223in field-effect transistor switches
H03K 3/012
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
01Details
012Modifications of generator to improve response time or to decrease power consumption
H03K 3/0375
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
027by the use of logic circuits, with internal or external positive feedback
037Bistable circuits
0375provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
H03K 5/19
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
19Monitoring patterns of pulse trains
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • CHEN, Wilson
  • TAN, Chiew-Guan
  • JALILIZEINALI, Reza
Agents
  • HALLMAN, Jonathan W.
Priority Data
15/197,58929.06.2016US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LATCH-BASED POWER-ON CHECKER
(FR) VÉRIFICATEUR DE MISE SOUS TENSION BASÉ SUR UN VERROU
Abstract
(EN)
A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX > CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.
(FR)
L'invention porte sur un circuit de vérification de mise sous tension (POC) basé sur un verrou, destiné à atténuer des problèmes potentiels provenant d'une séquence de mise sous tension inappropriée entre différents domaines d'alimentation (par exemple, cœur et entrée/sortie (E/S)) sur un circuit intégré (CI) de système sur puce (SoC). Dans un exemple, le domaine d'alimentation de cœur présentant une première tension (CX) devrait être mis sous tension avant le domaine d'alimentation E/S présentant une seconde tension (PX), avec PX > CX. Si PX croît avant CX, le circuit POC produit un signal indiquant une séquence de mise sous tension inappropriée, qui amène les plots E/S à être mis dans un état connu. Après que CX a crû subséquemment, le circuit POC revient à un état passif (LOW). Si CX devait ensuite s'effondrer alors que PX est encore haut, le circuit POC resterait LOW jusqu'à ce que PX s'effondre également.
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