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Pub. No.: WO/2018/004807 International Application No.: PCT/US2017/029471
Publication Date: 04.01.2018 International Filing Date: 25.04.2017
Chapter 2 Demand Filed: 01.09.2017
IPC:
H03K 17/22 (2006.01) ,G06F 1/24 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
22
Modifications for ensuring a predetermined initial state when the supply voltage has been applied
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
24
Resetting means
Applicants: QUALCOMM INCORPORATED[US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: CHEN, Wilson; US
TAN, Chiew-Guan; US
JALILIZEINALI, Reza; US
Agent: HALLMAN, Jonathan W.; US
Priority Data:
15/197,58929.06.2016US
Title (EN) LATCH-BASED POWER-ON CHECKER
(FR) VÉRIFICATEUR DE MISE SOUS TENSION BASÉ SUR UN VERROU
Abstract:
(EN) A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX > CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.
(FR) L'invention porte sur un circuit de vérification de mise sous tension (POC) basé sur un verrou, destiné à atténuer des problèmes potentiels provenant d'une séquence de mise sous tension inappropriée entre différents domaines d'alimentation (par exemple, cœur et entrée/sortie (E/S)) sur un circuit intégré (CI) de système sur puce (SoC). Dans un exemple, le domaine d'alimentation de cœur présentant une première tension (CX) devrait être mis sous tension avant le domaine d'alimentation E/S présentant une seconde tension (PX), avec PX > CX. Si PX croît avant CX, le circuit POC produit un signal indiquant une séquence de mise sous tension inappropriée, qui amène les plots E/S à être mis dans un état connu. Après que CX a crû subséquemment, le circuit POC revient à un état passif (LOW). Si CX devait ensuite s'effondrer alors que PX est encore haut, le circuit POC resterait LOW jusqu'à ce que PX s'effondre également.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)