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1. (WO2018004670) SPATIALLY SEGMENTED ILD LAYER FOR RRAM-COMPATIBLE ULTRA-SCALED LOGIC DEVICES

Pub. No.:    WO/2018/004670    International Application No.:    PCT/US2016/040771
Publication Date: Fri Jan 05 00:59:59 CET 2018 International Filing Date: Sat Jul 02 01:59:59 CEST 2016
IPC: H01L 45/00
Applicants: INTEL CORPORATION
Inventors: SUNG, Seung Hoon
PILLARISETTY, Ravi
SINGH, Kanwaljit
Title: SPATIALLY SEGMENTED ILD LAYER FOR RRAM-COMPATIBLE ULTRA-SCALED LOGIC DEVICES
Abstract:
Approaches for integrating resistive random access memory (RRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a first portion of an inter-layer dielectric (ILD) layer disposed above a first region of a substrate, and a resistive random access memory (RRAM) array disposed in a second portion of the ILD layer laterally adjacent to the first portion of the ILD layer. The second portion of the ILD layer has a higher dielectric constant than the first portion of the ILD layer.