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1. (WO2018004663) TWO TRANSISTOR MEMORY CELL WITH METAL OXIDE SEMICONDUCTORS AND SILICON TRANSISTORS

Pub. No.:    WO/2018/004663    International Application No.:    PCT/US2016/040742
Publication Date: Fri Jan 05 00:59:59 CET 2018 International Filing Date: Sat Jul 02 01:59:59 CEST 2016
IPC: H01L 27/115
G11C 16/04
Applicants: INTEL CORPORATION
Inventors: LE, Van H.
DEWEY, Gilbert William
RIOS, Rafael
KAVALIEROS, Jack T.
RADOSAVLJEVIC, Marko
SHIVARAMAN, Shriram
METERELLIYOZ, Mesut
Title: TWO TRANSISTOR MEMORY CELL WITH METAL OXIDE SEMICONDUCTORS AND SILICON TRANSISTORS
Abstract:
A two transistor memory cell is described with amorphous oxide semiconductors and silicon transistors. In some examples a memory cell includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.