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1. (WO2018004653) BACKSIDE CONTACT RESISTANCE REDUCTION FOR SEMICONDUCTOR DEVICES WITH METALLIZATION ON BOTH SIDES

Pub. No.:    WO/2018/004653    International Application No.:    PCT/US2016/040688
Publication Date: Fri Jan 05 00:59:59 CET 2018 International Filing Date: Sat Jul 02 01:59:59 CEST 2016
IPC: H01L 29/78
H01L 29/66
H01L 21/8234
Applicants: INTEL CORPORATION
Inventors: GLASS, Glenn A.
MURTHY, Anand S.
JAMBUNATHAN, Karthik
MOHAPATRA, Chandra S.
KOBRINSKY, Mauro J.
MORROW, Patrick
Title: BACKSIDE CONTACT RESISTANCE REDUCTION FOR SEMICONDUCTOR DEVICES WITH METALLIZATION ON BOTH SIDES
Abstract:
Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.