Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.