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1. (WO2018004578) SUPERCONDUCTOR-SILICON INTERFACE CONTROL
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2018/004578 International Application No.: PCT/US2016/040244
Publication Date: 04.01.2018 International Filing Date: 30.06.2016
IPC:
H01L 29/12 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
ROBERTS, Jeanette M.; US
PILLARISETTY, Ravi; US
YOSCOVITS, Zachary R.; US
CLARKE, James S.; US
MICHALAK, David J.; US
Agent:
HARTMANN, Natalya; US
Priority Data:
Title (EN) SUPERCONDUCTOR-SILICON INTERFACE CONTROL
(FR) COMMANDE D'INTERFACE SUPRACONDUCTEUR-SILICIUM
Abstract:
(EN) Described herein are methods that allow reducing or eliminating formation of silicon nitride layers at superconductor-silicon interfaces, as well as quantum circuit devices fabricated using such methods. The methods include applying various surface modification techniques to silicon in order to form a controlled interfacial layer at the interface of silicon and superconductor, which interfacial layer prevents or at least minimizes formation of silicon nitride at said interface. Reducing or eliminating silicon nitride layers at superconductor-silicon interfaces in quantum circuits may help minimizing the negative effects of spurious TLS's, thereby improving on the decoherence problem of qubits.
(FR) L'invention concerne des procédés qui permettent de réduire ou d'éliminer la formation de couches de nitrure de silicium sur des interfaces supraconductrice-silicium, ainsi que des dispositifs à circuits quantiques fabriqués à l'aide de ces procédés. Les procédés comprennent l'application de diverses techniques de modification de surface au silicium afin de former une couche interfaciale contrôlée sur l'interface du silicium et du supraconducteur, ladite couche interfaciale empêchant ou au moins minimisant la formation de nitrure de silicium au niveau de ladite interface. La réduction ou l'élimination des couches de nitrure de silicium au niveau des interfaces supraconducteur-silicium dans les circuits quantiques peut aider à minimiser les effets négatifs de parasites TLS, ce qui permet d'améliorer le problème de décohérence des qubits.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20190131511