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1. (WO2018004562) APPROACHES FOR FABRICATING SELF-ALIGNED PEDESTALS FOR RRAM DEVICES AND THE RESULTING STRUCTURES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/004562 International Application No.: PCT/US2016/040030
Publication Date: 04.01.2018 International Filing Date: 29.06.2016
IPC:
G11C 13/00 (2006.01) ,H01L 27/10 (2006.01) ,H01L 45/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
13
Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
MAJHI, Prashant; US
INDUKURI, Tejaswi K.; US
PILLARISETTY, Ravi; US
SHAH, Uday; US
MUKHERJEE, Niloy; US
KARPOV, Elijah V.; US
CLARKE, James S.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) APPROACHES FOR FABRICATING SELF-ALIGNED PEDESTALS FOR RRAM DEVICES AND THE RESULTING STRUCTURES
(FR) APPROCHES POUR FABRIQUER DES SOCLES AUTO-ALIGNÉS POUR DES DISPOSITIFS RRAM ET STRUCTURES RÉSULTANTES
Abstract:
(EN) Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the conductive interconnect and in the ILD layer. The first electrode layer has an uppermost surface substantially co-planar with an uppermost surface of the ILD layer. A resistance switching layer is disposed on the uppermost surface of the first electrode layer and on a portion of the uppermost surface of the ILD layer. A second electrode layer is disposed on the resistance switching layer.
(FR) L'invention porte également sur des approches pour fabriquer des socles auto-alignés pour des éléments et des dispositifs de mémoire vive résistive (RRAM), et sur les structures résultantes. Dans un exemple, un dispositif de mémoire vive résistive (RRAM) comprend une interconnexion conductrice disposée dans une couche diélectrique inter-couche (ILD) disposée au-dessus d'un substrat. Un élément RRAM est disposé sur l'interconnexion conductrice. L'élément RRAM comprend une première couche d'électrode disposée sur l'interconnexion conductrice et dans la couche ILD. La première couche d'électrode présente une surface supérieure sensiblement coplanaire avec une surface supérieure de la couche ILD. Une couche à commutation de résistance est disposée sur la surface supérieure de la première couche d'électrode et sur une partie de la surface supérieure de la couche ILD. Une deuxième couche d'électrode est disposée sur la couche à commutation de résistance.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)