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1. WO2018004496 - A CONFIGURABLE LATCH CIRCUIT WITH LOW LEAKAGE CURRENT AND INSTANT TRIGGER INPUT

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

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CLAIMS

A latch circuit (1), which is connected between a power source and a load, which can be adjusted such that it will be latched/not latched depending on the configuration of the switches during application of the power for the first time, which can be closed again in a certain time after it is latched, essentially characterized by

a first MOSFET (Qi) which is connected between an input port (2) to which the power source to be switched to the source terminal (S) is connected and an output port (3) to which the loads to be switched on and off by being switched to the drain terminal (D),

- a fourth switch (SW4) which is connected between the input port (2) and the source terminal (S) of the first MOSFET (Qj),

- a first switch (SWi) one terminal of which is between the fourth switch (SW4) and the source terminal (S) of the first MOSFET (Qi), and the other terminal of which is connected to the gate terminal (G) of the first MOSFET (Qi) through a first capacitor (Ci),

- a trigger port (4) which is connected to the gate terminal (G) of the first MOSFET (Qi) through a second resistor (R2), and to which the instantaneous trigger input is given,

- a second MOSFET (Q2) the drain terminal (D) of which is connected to the gate terminal (G) of the first MOSFET (Qi) through a third resistor (R3), and the source terminal (S) of which is connected to the ground,

- a second capacitor (C2) which is connected between the drain terminal (D) of the second MOSFET (Q2) and the ground through a third switch (SW3),

- a second switch (SW2) which is connected in series to a fourth resistor (R4) on a branch parallel to a branch on which the third switch (SW3) is present,

- a third capacitor (C3) which is connected between the gate terminal (G) and the source terminal (S) of the second MOSFET (Q2),

- a third MOSFET (Q3) the drain terminal (D) of which is connected to the gate terminal (G) of the second MOSFET (Q2) through a sixth resistance (R6), and the source terminal (S) of which is connected to the ground,

- a fourth capacitor (C4) which is connected between the gate terminal (G) of the third MOSFET (Q3) and the ground,

- a suspension port (5) which is connected to the gate terminal (G) of the third MOSFET (Q3) through a ninth resistor (R9), and wherein the control signal is given in order to prevent the latched circuit from entering to the closed state again.

A latch circuit (1) according to claim 1, characterized by first resistor (Ri) which is connected between the source terminal (S) and gate terminal (G) of the first MOSFET (Ql), and third resistor (R3) which is connected between the gate terminal (G) of the first MOSFET (Qi) and the drain terminal (D) of the second MOSFET (Q2).

A latch circuit (1) according to claim 1, characterized by second resistor (R2) which is connected between the trigger port (4) and the gate terminal (G) of the first MOSFET (Qi), and which enables to limit the current to flow into the trigger port (4).

A latch circuit (1) according to claim 1, characterized by fourth resistor (R4) which is connected between the second switch (SW2) and the ground, and which enables the second capacitor (C2) to discharge.

A latch circuit (1) according to claim 1, characterized by fifth resistor (R5) one terminal of which is connected between the output port (3) and the drain terminal (D) of the first MOSFET (Qi), and the other terminal of which is connected to the gate terminal (G) of the second MOSFET (Q2), and a seventh resistor (R7) one terminal of which is connected to the gate terminal (G) of the second MOSFET (Q2) and the other terminal of which is connected to the ground.

6. A latch circuit (1) according to claim 5, characterized by sixth resistor (R6) which is connected between the gate terminal (G) of the second MOSFET

(Q2) and the drain terminal (D) of the third MOSFET (Q3), and the value of which is smaller than the value of the parallel equivalent resistance formed by the fifth resistor (R5) and the seventh resistor (R7).

7. A latch circuit (1) according to claim 1, characterized by eighth resistor (R8) which is connected between the output port (3) and the gate terminal (G) of the third MOSFET (Q3), and a tenth resistor (Rio) which is connected between the gate terminal (G) of the third MOSFET (Q3) and the ground.

8. A latch circuit (1) according to claim 7, characterized by ninth resistor (R9) which is connected between the suspension port (5) and the gate terminal (G) of the third MOSFET (Q3), and the value of which is smaller than the parallel equivalent resistance value formed by the eighth resistor (R8) and the tenth resistor (Rio).

9. A latch circuit (1) according to claim 1, characterized by fourth switch (SW4) which enables the input power to be applied/cut off.

10. A latch circuit (1) according to claim 9, characterized by first MOSFET (Qi) which can start conduction when the fourth switch (SW4) is closed.

11. A latch circuit (1) according to claim 10, characterized by second MOSFET (Q2) which starts conduction after the first MOSFET (Qi) starts conduction.

12. A latch circuit (1) according to claim 5, characterized by third capacitor (C3) the value of which increases to a level determined by the fifth resistor (R5), seventh resistor (R7) and output voltage (Vout) through the fifth resistor (R5) upon the second MOSFET (Q2) passing to the conduction.

13. A latch circuit (1) according to claim 1 or 2, characterized by first resistor (Ri) which keeps the first MOSFET (Qj) with the voltage dropped thereon by means of the current passing through the second MOSFET (Q2).

14. A latch circuit (1) according to claim 12, characterized by third MOSFET (Q3) which stops the conduction of the second MOSFET (Q2), when it is in conduction.

15. A latch circuit (1) according to claim 14, characterized by second MOSFET (Q2) which stops the conduction of the first MOSFET (Qi), when it stops its conduction.

16. A latch circuit (1) according to claim 1, characterized by suspension port (5) wherein low level voltage is applied enabling that the fourth capacitor (C4) cannot be charged through the eighth resistor (R8) in order to prevent the third MOSFET (Q3) from starting conduction.

17. A latch circuit (1) according to claim 1 or 16, characterized by suspension port (5) which can be left at floating level in order to enable the third MOSFET (Q3) to conduct and therefore inhibit the latch structure by charging the fourth capacitor (C4).

18. A latch circuit (1) according to claim 15, characterized by trigger port (4) to which the signal to activate the first MOSFET (Qi) for conduction for entering from Open Circuit state to Closed Circuit state.

19. A latch circuit (1) according to claim 15, characterized by trigger port (4) to which a high level trigger signal is given for closing the circuit before the third MOSFET (Q3) starts conduction.