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1. (WO2018003445) CAPACITOR
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Pub. No.: WO/2018/003445 International Application No.: PCT/JP2017/021240
Publication Date: 04.01.2018 International Filing Date: 08.06.2017
IPC:
H01G 4/12 (2006.01) ,H01G 4/33 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
018
Dielectrics
06
Solid dielectrics
08
Inorganic dielectrics
12
Ceramic dielectrics
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
33
Thin- or thick-film capacitors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
原田 真臣 HARADA, Masatomi; JP
泉谷 淳子 IZUMITANI, Junko; JP
香川 武史 KAGAWA, Takeshi; JP
石田 宣博 ISHIDA, Nobuhiro; JP
Agent:
稲葉 良幸 INABA, Yoshiyuki; JP
大貫 敏史 ONUKI, Toshifumi; JP
Priority Data:
2016-12804728.06.2016JP
Title (EN) CAPACITOR
(FR) CONDENSATEUR
(JA) キャパシタ
Abstract:
(EN) Provided is a capacitor comprising an upper electrode, a substrate, and a lower electrode, in which generation of substrate capacitance is prevented. A capacitor according to one aspect of the present invention is provided with a substrate, a lower electrode formed on the substrate, a dielectric film formed on the lower electrode, an upper electrode formed on a part of the dielectric film, and a first terminal electrode connecting to the upper electrode. The upper electrode and the first terminal electrode are formed in the region in which the lower electrode is formed when the capacitor is viewed in plan view from the first terminal electrode side.
(FR) L'invention concerne un condensateur comprenant une électrode supérieure, un substrat et une électrode inférieure, dans lesquels la génération de la capacité du substrat est empêchée. Un condensateur selon un aspect de la présente invention est pourvu d'un substrat, d'une électrode inférieure formée sur le substrat, d'un film diélectrique formé sur l'électrode inférieure, une électrode supérieure formée sur une partie du film diélectrique, et une première électrode terminale reliée à l'électrode supérieure. L'électrode supérieure et la première électrode terminale sont formées dans la région dans laquelle l'électrode inférieure est formée lorsque le condensateur est vu dans une vue en plan à partir du côté de la première électrode terminale.
(JA) 上部電極、基板、下部電極からなる基板容量の発生を防止したキャパシタを提供する。 本発明の一側面に係るキャパシタは、基板と、基板上に形成された下部電極と、下部電極上に形成された誘電体膜と、誘電体膜上の一部に形成された上部電極と、上部電極に接続する第1端子電極と、を備え、上部電極及び第1端子電極は、第1端子電極側からキャパシタを見た平面視において、下部電極の形成領域内に形成されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)