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1. (WO2018002763) TRANSISTOR AND SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/002763 International Application No.: PCT/IB2017/053576
Publication Date: 04.01.2018 International Filing Date: 16.06.2017
IPC:
H01L 29/786 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 398, Hase Atsugi-shi, Kanagawa 2430036, JP
Inventors:
YAMAZAKI, Shunpei; JP
Priority Data:
2016-12710027.06.2016JP
2016-14098018.07.2016JP
Title (EN) TRANSISTOR AND SEMICONDUCTOR DEVICE
(FR) TRANSISTOR ET DISPOSITIF À SEMI-CONDUCTEUR
Abstract:
(EN) A transistor includes a gate electrode, a first conductor, a second conductor, a gate insulator, and a metal oxide. The gate insulator is located between the gate electrode and the metal oxide. The gate electrode includes a region overlapping with the metal oxide with the gate insulator therebetween. The first conductor and the second conductor each include a region in contact with top and side surfaces of the metal oxide. The metal oxide has a layered structure in which oxides each having a first band gap and oxides each having a second band gap and being adjacent to the oxide having the first band gap are alternately stacked in a thickness direction. The metal oxide includes two or more oxides each having the first band gap. The first band gap is smaller than the second band gap.
(FR) L'invention concerne un transistor qui comprend une électrode de grille, un premier conducteur, un second conducteur, un isolant de grille et un oxyde métallique. L'isolant de grille est situé entre l'électrode de grille et l'oxyde métallique. L'électrode de grille comprend une région chevauchant l'oxyde métallique, l'isolant de grille se trouvant entre eux. Le premier conducteur et le second conducteur comprennent chacun une région en contact avec les surfaces supérieure et latérale de l'oxyde métallique. L'oxyde métallique présente une structure stratifiée dans laquelle des oxydes présentant chacun une première largeur de bande interdite et des oxydes présentant chacun une seconde largeur de bande interdite et étant adjacents à l'oxyde présentant la première largeur de bande interdite sont alternativement empilés dans une direction d'épaisseur. L'oxyde métallique comprend au moins deux oxydes présentant chacun la première largeur de bande interdite. La première largeur de bande interdite est plus étroite que la seconde largeur de bande interdite.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)