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1. (WO2018002742) VERTICAL FET DEVICES WITH MULTIPLE CHANNEL LENGTHS
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Pub. No.: WO/2018/002742 International Application No.: PCT/IB2017/053238
Publication Date: 04.01.2018 International Filing Date: 01.06.2017
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
IBM (CHINA) INVESTMENT COMPANY LIMITED [CN/CN]; 25/F, Pangu Plaza No.27, Central North 4th Ring Road, Chaoyang District, Beijing 100101, CN (MG)
Inventors:
VENIGALLA, Rajasekhar; US
VEGA, Reinaldo, Ariel; US
MALLELA, Hari; US
Agent:
LITHERLAND, David; GB
Priority Data:
15/197,85930.06.2016US
Title (EN) VERTICAL FET DEVICES WITH MULTIPLE CHANNEL LENGTHS
(FR) DISPOSITIFS TEC VERTICAUX À MULTIPLES LONGUEURS DE CANAL
Abstract:
(EN) A semiconductor device comprises a first source/drain region (802) arranged on a semiconductor substrate (102), a second source/drain region (1002) arranged on the semiconductor substrate (102), a bottom spacer (1602) arranged on the first source/drain region (802), and a bottom spacer (1602) arranged on the second source/drain region (1002). A first gate stack (2602a) having a first length (L1) is arranged on the first source/drain region (802). A second gate stack (2602b) having a second length (L2) is arranged on the second source/drain region (1002), the first length (L1) is shorter than the second length (L2). A top spacer (2702) is arranged on the first gate stack (2602a), and a top spacer (2702) is arranged on the second gate stack (2702b).
(FR) Selon l'invention, un dispositif semi-conducteur comprend une première région de source/drain (802) agencée sur un substrat semi-conducteur (102), une deuxième région de source/drain (1002) agencée sur le substrat semi-conducteur (102), un intercalaire inférieur (1602) agencé sur la première région de source/drain (802), et un intercalaire inférieur (1602) agencé sur la deuxième région de source/drain (1002). Un premier empilement de grille (2602a) ayant une première longueur (L1) est agencé sur la première région de source/drain (802). Un deuxième empilement de grille (2602b) ayant une deuxième longueur (L2) est agencé sur la deuxième région de source/drain (1002), la première longueur (L1) étant inférieure à la deuxième longueur (L2). Un intercalaire supérieur (2702) est agencé sur le premier empilement de grille (2602a), et un intercalaire supérieur (2702) est agencé sur le deuxième empilement de grille (2702b).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)