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1. (WO2018000357) POWER MOSFET WITH METAL FILLED DEEP SINKER CONTACT FOR CSP
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/000357 International Application No.: PCT/CN2016/087968
Publication Date: 04.01.2018 International Filing Date: 30.06.2016
IPC:
H01L 29/417 (2006.01) ,H01L 29/78 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants: TEXAS INSTRUMENTS INCORPORATED[US/US]; P.O.Box 655474 Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED[JP/JP]; 24-1 Nishi-Shinjuku 6-chome Shinjuku-ku, Tokyo 160-8366, JP (JP)
Inventors: LIU, Yunlong; CN
YANG, Hong; US
LIN, Ho; CN
LV, Tianping; CN
ZOU, Sheng; CN
JIA, Qiuling; CN
XIONG, Yufei; CN
Agent: JEEKAI & PARTNERS; Floor 15A, Building No. 5, GTFC Plaza 9 Guang'an Road, Fengtai District Beijing 100055, CN
Priority Data:
Title (EN) POWER MOSFET WITH METAL FILLED DEEP SINKER CONTACT FOR CSP
(FR) TRANSISTOR À EFFET DE CHAMP MÉTAL-OXYDE SEMICONDUCTEUR DE PUISSANCE À CONTACT DE PUITS COLLECTEUR PROFOND REMPLI DE MÉTAL POUR CSP
Abstract:
(EN) A method of forming an IC (180) including a power semiconductor device includes providing a substrate (100) having an epi layer (150) thereon with at least one transistor (160) formed therein covered by a pre-metal dielectric (PMD) layer (118). Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material (128b) is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer (128c) is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact (128). A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.
(FR) L'invention porte sur un procédé de formation d'un circuit intégré (CI) (180) comprenant un dispositif à semi-conducteur de puissance, qui consiste à prendre un substrat (100) comportant sur lui une couche épitaxiale (150) dans laquelle est formée au moins un transistor (160) recouvert d'une couche de diélectrique pré-métal (DMP). Des ouvertures de contact sont gravées à travers le PMD jusque dans la couche épitaxiale pour former une tranchée de puits collecteur s'étendant jusqu'à un premier nœud du dispositif. Un matériau de remplissage métallique (128b) est déposé pour recouvrir une paroi latérale et un fond de la tranchée de puits collecteur, mais ne remplit pas complètement la tranchée de puits collecteur. Une couche de charge diélectrique (128c) est déposée sur le matériau de remplissage métallique pour remplir la tranchée de puits collecteur. Une région de couverture de la couche de charge diélectrique est éliminée en s'arrêtant sur une surface du matériau de remplissage métallique dans la région de couverture afin de former un contact de puits collecteur (128). Un métal d'interconnexion à motifs est formé, assurant une connexion entre le métal d'interconnexion et le matériau de remplissage métallique sur la paroi latérale de la tranchée de puits collecteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)