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1. WO2017209842 - MULTIPLE CYCLE SEARCH CONTENT ADDRESSABLE MEMORY

Publication Number WO/2017/209842
Publication Date 07.12.2017
International Application No. PCT/US2017/027110
International Filing Date 12.04.2017
Chapter 2 Demand Filed 13.03.2018
IPC
G11C 15/00 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G11C 15/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G11C 15/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
G11C 15/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • TONG, Kim Yaw
  • VENKUMAHANTI, Suresh Kumar
  • HAMDAN, Fadi
  • MA, Kun
Agents
  • GELFOUND, Craig, A.
  • HODGES, Jonas J.
  • HARRIMAN, John D.
  • BINDSEIL, James
Priority Data
15/369,82305.12.2016US
62/343,67131.05.2016US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MULTIPLE CYCLE SEARCH CONTENT ADDRESSABLE MEMORY
(FR) MÉMOIRE ADRESSABLE PAR LE CONTENU À RECHERCHE EN PLUSIEURS CYCLES
Abstract
(EN)
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.
(FR)
Un aspect de l'invention concerne un procédé et un appareil. L'appareil peut être une mémoire adressable par le contenu. La mémoire adressable par le contenu comprend une pluralité de sections de mémoire, chacune de ces sections étant configurée pour mémoriser des données. De plus, la mémoire adressable par le contenu inclut un comparateur conçu pour comparer les données mémorisées dans chacune de la pluralité de sections de mémoire à des données d'entrée de recherche. La comparaison peut être effectuée de manière multiplexée dans le temps. Le comparateur peut servir à comparer les données mémorisées dans chacune des sections de mémoire à des données d'entrée de recherche dans un cycle correspondant d'une pluralité de cycles d'accès à la mémoire. La mémoire adressable par le contenu peut comporter un automate d'états destiné à assurer la commande lorsque le comparateur compare les données mémorisées dans chacune des sections de mémoire aux données d'entrée de recherche sur la base d'un état de l'automate d'états.
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