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1. (WO2017204966) DYNAMIC CLOCK GATING FREQUENCY SCALING

Pub. No.:    WO/2017/204966    International Application No.:    PCT/US2017/029154
Publication Date: Fri Dec 01 00:59:59 CET 2017 International Filing Date: Tue Apr 25 01:59:59 CEST 2017
IPC: G06F 1/08
G06F 1/26
G06F 3/06
Applicants: INTEL CORPORATION
Inventors: ROYCHOWDHURY, Arojit
DURG, Ajaya
HUDDAR, Shilpa
SHANBHAG, Sunil
SARURKAR, Vishram
SINGH, Tejpal
Title: DYNAMIC CLOCK GATING FREQUENCY SCALING
Abstract:
An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.