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1. (WO2017204937) METHOD OF INTEGRATING FINFET CMOS DEVICES WITH EMBEDDED NONVOLATILE MEMORY CELLS
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Pub. No.: WO/2017/204937 International Application No.: PCT/US2017/028034
Publication Date: 30.11.2017 International Filing Date: 18.04.2017
IPC:
H01L 29/66 (2006.01) ,H01L 29/792 (2006.01) ,H01L 29/788 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
Applicants:
SILICON STORAGE TECHNOLOGY, INC. [US/US]; 450 Holger Way San Jose, CA 95134, US
Inventors:
SU, Chien-Sheng; US
YANG, Jeng-Wei; TW
WU, Man-Tang; TW
CHEN, Chun-Ming; TW
TRAN, Hieu, Van; US
DO, Nhan; US
Agent:
LIMBACH, Alan, A.; US
Priority Data:
15/489,54817.04.2017US
62/341,00524.05.2016US
Title (EN) METHOD OF INTEGRATING FINFET CMOS DEVICES WITH EMBEDDED NONVOLATILE MEMORY CELLS
(FR) PROCÉDÉS D'INTÉGRATION DE DISPOSITIFS FINFET CMOS À DES CELLULES DE MÉMOIRE NON VOLATILE INCORPORÉES
Abstract:
(EN) A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.
(FR) L'invention porte sur un procédé de formation d'un dispositif de mémoire ayant des cellules de mémoire sur une surface plane d'un substrat et des dispositifs logiques FinFET sur des parties de surface en forme d'ailettes du substrat, ledit procédé consistant à former une couche de protection sur des grilles flottantes, des grilles d'effacement, du polysilicium de ligne de mot et des zones de source précédemment formés dans une partie cellules de mémoire du substrat, puis à former des ailettes dans la surface du substrat et à former des portes logiques le long des ailettes dans une partie logique du substrat, puis à éliminer la couche de protection et à achever la formation de grilles de ligne de mot à partir du polysilicium de ligne de mot et de zones de drain dans la partie cellules de mémoire du substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)