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1. (WO2017204821) SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS

Pub. No.:    WO/2017/204821    International Application No.:    PCT/US2016/034624
Publication Date: Fri Dec 01 00:59:59 CET 2017 International Filing Date: Sat May 28 01:59:59 CEST 2016
IPC: H01L 21/768
Applicants: INTEL CORPORATION
Inventors: LIN, Kevin
BRISTOL, Robert L.
SCHENKER, Richard E.
Title: SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS
Abstract:
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.