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1. (WO2017203928) METHOD FOR MANUFACTURING LEAD FRAME, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE
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Pub. No.: WO/2017/203928 International Application No.: PCT/JP2017/016571
Publication Date: 30.11.2017 International Filing Date: 26.04.2017
IPC:
H01L 23/50 (2006.01) ,H01L 21/56 (2006.01) ,H01L 25/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50
for integrated circuit devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Applicants: SONY CORPORATION[JP/JP]; 1-7-1 Konan, Minato-ku, Tokyo 1080075, JP
Inventors: HOSOKAWA, Koyo; JP
OZAKI, Hiroshi; JP
Agent: OMORI, Junichi; JP
Priority Data:
2016-10600227.05.2016JP
Title (EN) METHOD FOR MANUFACTURING LEAD FRAME, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE
(FR) MÉTHODE DE FABRICATION DE GRILLE DE CONNEXION, MÉTHODE DE FABRICATION DE DISPOSITIFS ÉLECTRONIQUES ET DISPOSITIFS ÉLECTRONIQUES
(JA) リードフレームの製造方法、電子装置の製造方法、および電子装置
Abstract:
(EN) [Problem] To provide a method for manufacturing a lead frame with which connection terminals can be arranged in multiple rows around a circuit chip without requiring complex manufacturing processes or a large number of steps. [Solution] A method for manufacturing a lead frame according to one embodiment of the present invention includes affixing a tape member to at least a lead frame member having a lead frame rim. A lead frame part including a die pad and/or a connection terminal is mounted on the tape member inside the lead frame brim.
(FR) [problème] fournir une méthode pour fabriquer une grille de connexion avec laquelle des bornes de connexion peuvent être agencées en plusieurs rangées autour d'une puce de circuit sans nécessiter de processus de fabrication complexes ou un grand nombre d'étapes. [Solution] une méthode pour fabriquer une grille de connexion selon un mode de réalisation de la présente invention qui comprend la fixation d'un élément de bande à au moins un élément de grille de connexion ayant une bordure de grille de connexion. Une partie de grille de connexion comprenant une plage de connexion et/ou une borne de connexion est montée sur l'élément de bande à l'intérieur du bord de la grille de connexion.
(JA) 【課題】複雑な製造プロセスおよび多くの工程数を必要とせず、回路チップの周囲の接続端子の多列化が可能なリードフレームの製造方法を提供すること。 【解決手段】本技術の一形態に係るリードフレームの製造方法は、少なくともリードフレーム枠を有するリードフレーム部材にテープ部材を貼り付けることを含む。前記リードフレーム枠内の前記テープ部材に、ダイパッドおよび接続端子のうち少なくとも一方を含むリードフレームパーツが搭載される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)