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1. (WO2017203186) INTEGRATED CIRCUIT COMPRISING A CHIP FORMED BY A HIGH-VOLTAGE TRANSISTOR AND COMPRISING A CHIP FORMED BY A LOW-VOLTAGE TRANSISTOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2017/203186    International Application No.:    PCT/FR2017/051315
Publication Date: 30.11.2017 International Filing Date: 26.05.2017
IPC:
H01L 25/18 (2006.01), H03K 17/082 (2006.01)
Applicants: EXAGAN [FR/FR]; 7 Parvis Louis Néel BP 50 38040 Grenoble Cedex 9 (FR)
Inventors: MOREAU, Eric; (FR).
SUTTO, Thierry; (FR).
GUILLOT, Laurent; (FR)
Agent: BREESE, Pierre; (FR)
Priority Data:
1654715 26.05.2016 FR
1656572 08.07.2016 FR
Title (EN) INTEGRATED CIRCUIT COMPRISING A CHIP FORMED BY A HIGH-VOLTAGE TRANSISTOR AND COMPRISING A CHIP FORMED BY A LOW-VOLTAGE TRANSISTOR
(FR) CIRCUIT INTÉGRÉ COMPRENANT UNE PUCE FORMÉE D'UN TRANSISTOR À HAUTE TENSION ET COMPRENANT UNE PUCE FORMÉE D'UN TRANSISTOR À BASSE TENSION
Abstract: front page image
(EN)The invention relates to an integrated circuit (3) comprising a housing (4) and a plurality of connection pins, a first chip (1) that includes a high-voltage depletion mode transistor, and a second chip (2) that includes a low-voltage enhancement mode transistor, the first chip and second chip each comprising a gate bump contact (13, 23), drain bump contact (11, 21) and source bump contact (12, 22); the source bump contact (12) of the high-voltage transistor being electrically connected to the drain bump contact (21) of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin (36) that is electrically connected to the source bump contact (22) of the low-voltage transistor.
(FR)L'invention porte sur un circuit intégré (3) comprenant un boîtier (4) et une pluralité de broches de connexion, une première puce (1) comprenant un transistor à haute tension en mode déplétion et une deuxième puce (2) comprenant un transistor à basse tension en mode enrichissement, la première et la deuxième puce comportant respectivement des plots de contact de grille (13, 23), de drain (11, 21) et de source (12, 22); le plot de contact de source (12) du transistor à haute tension étant relié électriquement au plot de contact de drain (21) du transistor à basse tension pour former ainsi un nœud milieu du circuit. Le circuit comprend au moins une première broche kelvin (36) électriquement reliée au plot de contact de source (22) du transistor à basse tension.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: French (FR)
Filing Language: French (FR)