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1. (WO2017200703) PASSIVE COMPONENTS IMPLEMENTED ON A PLURALITY OF STACKED INSULATORS
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Pub. No.: WO/2017/200703 International Application No.: PCT/US2017/028862
Publication Date: 23.11.2017 International Filing Date: 21.04.2017
Chapter 2 Demand Filed: 26.09.2017
IPC:
H03H 7/01 (2006.01) ,H03H 1/00 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
7
Multiple-port networks comprising only passive electrical elements as network components
01
Frequency selective two-port networks
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
1
Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
YUN, Changhan Hobie; US
KIM, Daeik Daniel; US
KIM, Jonghae; US
VELEZ, Mario Francisco; US
ZUO, Chengjie; US
BERDY, David Francis; US
Agent:
OLDS, Mark E.; US
CICCOZZI, John L.; US
PODHAJNY, Daniel; US
Priority Data:
15/161,15220.05.2016US
Title (EN) PASSIVE COMPONENTS IMPLEMENTED ON A PLURALITY OF STACKED INSULATORS
(FR) COMPOSANTS PASSIFS MIS EN ŒUVRE SUR UNE PLURALITÉ D'ISOLANTS EMPILÉS
Abstract:
(EN) The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator (201), the first insulator being substantially planar and having a first top surface (201t) and a first bottom surface (201b) opposite the first top surface, a first conductor (211, 212) disposed on the first insulator, a second insulator (202), the second insulator being substantially planar and having a second top surface (202t) and a second bottom surface (202b) opposite the second top surface, a second conductor disposed on the second insulator (221, 222), and a dielectric layer (251) disposed between the first bottom conductor (212) of the first insulator (201) and the second top conductor (221) of the second insulator (202).
(FR) La présente invention concerne des appareils à circuit intégré et des procédés de fabrication d'appareils à circuit intégré. Un appareil à circuit intégré peut comprendre un premier isolant (201), le premier isolant étant sensiblement plan et présentant une première surface supérieure (201t) et une première surface inférieure (201b) opposée à la première surface supérieure ; un premier conducteur (211, 212) placé sur le premier isolant, un second isolant (202), le second isolant étant sensiblement plan et présentant une seconde surface supérieure (202t) et une seconde surface inférieure (202b) opposée à la seconde surface supérieure, un second conducteur placé sur le second isolant (221, 222), et une couche diélectrique (251) placée entre le premier conducteur inférieur (212) du premier isolant (201) et le second conducteur supérieur (221) du second isolant (202).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)