WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2017200701) DOUBLE-SIDED CIRCUIT
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2017/200701    International Application No.:    PCT/US2017/028851
Publication Date: 23.11.2017 International Filing Date: 21.04.2017
Chapter 2 Demand Filed:    15.03.2018    
IPC:
H03H 7/01 (2006.01), H03H 7/09 (2006.01), H01P 1/203 (2006.01), H05K 1/18 (2006.01), H01F 5/00 (2006.01), H01F 41/04 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 (US)
Inventors: YUN, Changhan Hobie; (US).
BERDY, David Francis; (US).
ZUO, Chengjie; (US).
KIM, Daeik Daniel; (US).
KIM, Jonghae; (US).
VELEZ, Mario Francisco; (US).
MUDAKATTE, Niranjan Sunil; (US).
MIKULKA, Robert Paul; (US)
Agent: OLDS, Mark E.; (US).
CICCOZZI, John L.; (US).
PODHAJNY, Daniel; (US)
Priority Data:
15/161,138 20.05.2016 US
Title (EN) DOUBLE-SIDED CIRCUIT
(FR) CIRCUIT À DOUBLE FACE
Abstract: front page image
(EN)The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.
(FR)La présente invention concerne des circuits et des procédés pour fabriquer les circuits. Un circuit peut comprendre un isolant ayant une première surface, une deuxième surface, une périphérie, un premier sous-ensemble d’éléments de circuit disposés sur la première surface, un deuxième sous-ensemble d’éléments de circuit disposés sur la deuxième surface, et au moins une paroi latérale conductrice disposée sur la périphérie, la paroi latérale conductrice couplant électriquement le premier sous-ensemble d’éléments de circuit au deuxième sous-ensemble d’éléments de circuit.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)