Search International and National Patent Collections

1. (WO2017200159) OVERLAY MARK, AND OVERLAY MEASUREMENT METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING SAME

Pub. No.:    WO/2017/200159    International Application No.:    PCT/KR2016/011584
Publication Date: Fri Nov 24 00:59:59 CET 2017 International Filing Date: Sat Oct 15 01:59:59 CEST 2016
IPC: G03F 7/20
G03F 9/00
G03F 1/42
H01L 23/544
Applicants: AUROS TECHNOLOGY, INC.
(주)오로스 테크놀로지
Inventors: CHANG, Hyun Jin
장현진
HA, Ho Cheul
하호철
LEE, Ghil Soo
이길수
Title: OVERLAY MARK, AND OVERLAY MEASUREMENT METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING SAME
Abstract:
The present invention relates to an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the same. The present invention provides an overlay mark for determining the relative shift between two successive pattern layers or between two or more patterns separately formed on a single layer, the overlay mark comprising: a first overlay structure that includes a pair of first bars facing one another and extending in a first direction, and a pair of second bars facing one another and extending in a second direction that is orthogonal to the first direction; and a second overlay structure that includes a plurality of pairs of third bars parallel to the first bars, and a plurality of pairs of fourth bars parallel to the second bars, wherein the gaps between neighbouring third bars are different from one another, and the gaps between neighbouring fourth bars are different from one another. The overlay mark according to the present invention has different gaps between bars, thereby being capable of minimising the occurrence of errors during image analysis.