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1. (WO2017199468) METHOD FOR FORMING INTERNAL STRESS CONTROL FILM
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/199468 International Application No.: PCT/JP2017/002484
Publication Date: 23.11.2017 International Filing Date: 25.01.2017
IPC:
C23C 14/34 (2006.01) ,C23C 14/06 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/285 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01)
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
22
characterised by the process of coating
34
Sputtering
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
06
characterised by the coating material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
285
from a gas or vapour, e.g. condensation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
株式会社アルバック ULVAC, INC. [JP/JP]; 神奈川県茅ケ崎市萩園2500 2500, Hagisono, Chigasaki-shi, Kanagawa 2538543, JP
Inventors:
中野 賢明 NAKANO Katsuaki; JP
平松 大典 HIRAMATSU Daisuke; JP
沼田 幸展 NUMATA Yukinobu; JP
Agent:
志賀 正武 SHIGA Masatake; JP
鈴木 慎吾 SUZUKI Shingo; JP
Priority Data:
2016-09815816.05.2016JP
Title (EN) METHOD FOR FORMING INTERNAL STRESS CONTROL FILM
(FR) PROCÉDÉ DE FORMATION DE FILM DE RÉGULATION DES CONTRAINTES INTERNES
(JA) 内部応力制御膜の形成方法
Abstract:
(EN) This method for forming an internal stress control film forms an internal stress control film on one surface of an object to be treated by sputtering. The pressure of a process gas used in forming the internal stress control film is selected from a pressure range which is higher than a threshold value 5 (Pa). This method forms an internal stress control film with high density in which when a bias is applied to the object, the stress to the object is more tensile than when no bias is applied.
(FR) Cette invention concerne un procédé de formation d'un film de régulation des contraintes internes, comprenant la formation d'un film de régulation des contraintes internes sur une surface d'un objet à traiter par pulvérisation. La pression d'un gaz de traitement utilisé pour former le film de régulation des contraintes internes est sélectionnée dans une plage de pressions qui est supérieure à une valeur seuil de 5 (Pa). Ce procédé forme un film de régulation des contraintes internes de haute densité dans lequel lorsqu'une sollicitation est appliquée à l'objet, la contrainte sur l'objet est plus élastique que dans le cas où aucune sollicitation n'est appliquée.
(JA) 内部応力制御膜の形成方法は、スパッタリング法により被処理体の一面に内部応力制御膜を形成し、前記内部応力制御膜を成膜する際のプロセスガスの圧力が、閾値5(Pa)より高い圧力領域から選択され、かつ、前記被処理体にBiasを印加した際の被処理体のStressがBiasを印加しない場合のStressに比べてTensile側に大きなStressであり、高い密度を有する内部応力制御膜を形成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)