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1. (WO2017197913) THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE USING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/197913 International Application No.: PCT/CN2017/070622
Publication Date: 23.11.2017 International Filing Date: 09.01.2017
IPC:
H01L 27/12 (2006.01)
Applicants: BOE TECHNOLOGY GROUP CO., LTD.[CN/CN]; No.10 Jiuxianqiao Rd. Chaoyang District Beijing 100015, CN
Inventors: LONG, Chunping; CN
QIAO, Yong; CN
Agent: CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; Suite 4-1105 No. 87 West 3rd Ring North Rd. Haidian District, Beijing 100089, CN
Priority Data:
201620442368.816.05.2016CN
Title (EN) THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE USING SAME
(FR) SUBSTRAT DE MATRICE DE TRANSISTORS À COUCHE MINCE ET DISPOSITIF D’AFFICHAGE UTILISANT CELUI-CI
(ZH) 薄膜晶体管阵列基板及其显示装置
Abstract: front page image
(EN) Provided are a thin film transistor array substrate and a display device using same. The thin film transistor array substrate comprises: a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, an active layer (30) thereof and the first signal line being located at different layers above the substrate, and projections of the active layer and the first signal line overlapping at least twice on a plane of the substrate. The thin film transistor array substrate has improved wiring efficiency and reliability.
(FR) L'invention concerne un substrat de matrice de transistors à couche mince et un dispositif d’affichage utilisant celui-ci. Le substrat de matrice de transistors à couche mince comprend : un substrat ; une première ligne de signal formée sur le substrat ; et un transistor à couche mince formé sur le substrat, une couche active (30) de celui-ci et la première ligne de signal étant situées au niveau de différentes couches au-dessus du substrat, et des saillies de la couche active et la première ligne de signal se chevauchant au moins deux fois sur un plan du substrat. Le substrat de matrice de transistors à couche mince présente une efficacité et une fiabilité de câblage améliorées.
(ZH) 一种薄膜晶体管阵列基板及应用其的显示装置,该薄膜晶体管阵列基板包括:基板;第一信号线,形成于基板上;以及薄膜晶体管,形成于基板上,其有源层(30)与所述第一信号线处于基板上方不同的层,两者在基板平面上的投影至少两次重叠。所述薄膜晶体管阵列基板可以提升薄膜晶体管阵列基板的布线效率和可靠性。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)