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1. (WO2017195874) MEMORY DEVICE AND MEMORY SYSTEM
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Pub. No.: WO/2017/195874 International Application No.: PCT/JP2017/017943
Publication Date: 16.11.2017 International Filing Date: 11.05.2017
IPC:
G11C 15/04 (2006.01) ,G06F 12/00 (2006.01) ,G11C 5/14 (2006.01) ,G11C 14/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
15
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04
using semiconductor elements
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
14
Power supply arrangements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
14
Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
Applicants: TOHOKU UNIVERSITY[JP/JP]; 2-1-1, Katahira, Aoba-ku, Sendai-shi, Miyagi 9808577, JP
Inventors: MA Yitao; JP
ENDOH Tetsuo; JP
Agent: YOSHIDA Tadanori; JP
Priority Data:
2016-09750013.05.2016JP
2016-09750113.05.2016JP
Title (EN) MEMORY DEVICE AND MEMORY SYSTEM
(FR) DISPOSITIF DE MÉMOIRE ET SYSTÈME DE MÉMOIRE
(JA) メモリ装置及びメモリシステム
Abstract:
(EN) Provided are the following: a memory device that has a compact circuit structure and can flexibly support the number of dimensions of reference data when retrieving data similar to search data; and a memory system. Provided is the memory system which is capable of reducing the processing time when retrieving data similar to search data, and which enables the circuit surface area to be reduced. A memory device 100 comprises: a plurality of read/write circuits 114 serving as reading circuits; an input search data storage circuit 131 which divides and outputs search data; a plurality of similarity evaluation cells 133; and a plurality of current integration circuits 135. The memory system is configured so as to be provided with a main core and a branch core with a configuration such as the foregoing.
(FR) L'invention concerne : un dispositif de mémoire qui a une structure de circuit compacte et peut supporter de manière flexible le nombre de dimensions de données de référence lors de la récupération de données similaires à des données de recherche ; et un système de mémoire. L'invention concerne un système de mémoire qui est susceptible de réduire le temps de traitement lors de la récupération de données similaires à des données de recherche, et qui permet de réduire la surface spécifique du circuit. Un dispositif de mémoire (100) comprend : une pluralité de circuits de lecture/écriture (114) servant de circuits de lecture ; un circuit de mémorisation de données de recherche d'entrée (131) qui divise et sort des données de recherche ; une pluralité de cellules d'évaluation de similarité (133) ; et une pluralité de circuits d'intégration de courant (135). Le système de mémoire est configuré de manière à être pourvu d'un cœur principal et d'un cœur de dérivation ayant une configuration décrite ci-dessus.
(JA) 検索データに類似するデータを探索する際に、参照データの次元数に柔軟に対応することができかつコンパクトな回路構成を有するメモリ装置及びメモリシステムを提供する。検索データに類似するデータを探索する際に処理時間を低減し、回路面積の低減が可能なメモリシステムを提供する。メモリ装置100は、複数の読み出し回路としての読出/書込回路114と、検索データを分けて出力する入力検索データ保存回路131と、複数の類似度評価セル133と、複数の電流統合回路135と、を備える。このような構成のメインコア及びブランチコアを備えることでメモリシステムを構成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)