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1. (WO2017193667) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS
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Pub. No.: WO/2017/193667 International Application No.: PCT/CN2017/074772
Publication Date: 16.11.2017 International Filing Date: 24.02.2017
IPC:
H01L 29/786 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/12 (2006.01) ,H01L 29/08 (2006.01) ,H01L 29/10 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
08
with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No. 10 Jiuxianqiao Rd. Chaoyang District Beijing 100015, CN
北京京东方显示技术有限公司 BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国北京市 经济技术开发区经海一路118号 No. 118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors:
白金超 BAI, Jinchao; CN
郭会斌 GUO, Huibin; CN
洪永泰 HONG, Young Tae; CN
Agent:
北京市柳沈律师事务所 LIU, SHEN & ASSOCIATES; 中国北京市 海淀区彩和坊路10号1号楼10层 10th Floor, Building 1 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201610311349.611.05.2016CN
Title (EN) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, SUBSTRAT MATRICIEL ET SON PROCÉDÉ DE FABRICATION, ET APPAREIL D'AFFICHAGE
(ZH) 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
Abstract:
(EN) A thin film transistor and a manufacturing method therefor, an array substrate and a manufacturing method therefor, and a display apparatus. The thin film transistor (100) comprises an active layer (110), an amorphous silicon connection layer (120) and a source-drain electrode layer (130). The active layer (110) has a channel region (113), a source region (111) and a drain region (112). The composite material of the channel region (113) comprises polysilicon. The amorphous silicon connection layer (120) is located at one side of the active layer (110), and comprises a first connection part (121) and a second connection part (122) which are arranged at intervals to each other. The source-drain electrode layer (130) comprises a source (131) and a drain (132) which are arranged at intervals to each other. The source (131) is electrically connected to the source region (111) via the first connection part (121), and the drain (132) is electrically connected to the drain region (112) via the second connection part (122). The manufacturing process for a polycrystalline silicon thin film transistor can be simplified.
(FR) La présente invention concerne un transistor à couches minces et son procédé de fabrication, un substrat matriciel et son procédé de fabrication, et un appareil d'affichage. Le transistor à couches minces (100) comprend une couche active (110), une couche de connexion en silicium amorphe (120) et une couche d'électrodes de source-drain (130). La couche active (110) comporte une zone de canal (113), une zone de source (111) et une zone de drain (112). Le matériau composite de la zone de canal (113) comprend du polysilicium. La couche de connexion en silicium amorphe (120) est située d'un côté de la couche active (110), et comprend une première partie de connexion (121) et une seconde partie de connexion (122) qui sont disposées à intervalles l'une de l'autre. La couche d'électrodes de source-drain (130) comprend une source (131) et un drain (132) qui sont disposés à intervalles l'un de l'autre. La source (131) est électriquement connectée à la zone de source (111) par l'intermédiaire de la première partie de connexion (121), et le drain (132) est électriquement connecté à la zone de drain (112) par l'intermédiaire de la seconde partie de connexion (122). Le processus de fabrication d'un transistor à couches minces au silicium polycristallin peut être simplifié.
(ZH) 一种薄膜晶体管及其制作方法、阵列基板及其制作方法和显示装置,薄膜晶体管(100)包括有源层(110)、非晶硅连接层(120)和源漏电极层(130)。有源层(110)具有沟道区(113)、源极区(111)和漏极区(112),沟道区(113)的形成材料包括多晶硅;非晶硅连接层(120)位于有源层(110)的一侧,并且包括彼此间隔设置的第一连接部(121)和第二连接部(122);源漏电极层(130)包括彼此间隔设置的源极(131)和漏极(132),源极(131)通过第一连接部(121)与源极区(111)电连接,漏极(132)通过第二连接部(122)与漏极区(112)电连接。可以简化多晶硅薄膜晶体管的制作工艺。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)