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1. (WO2017192626) INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/192626 International Application No.: PCT/US2017/030695
Publication Date: 09.11.2017 International Filing Date: 02.05.2017
IPC:
G11C 29/42 (2006.01) ,G06F 11/10 (2006.01) ,G11C 11/409 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
04
Detection or location of defective memory elements
08
Functional testing, e.g. testing during refresh, power-on self testing (POST) or distributed testing
12
Built-in arrangements for testing, e.g. built-in self testing (BIST)
38
Response verification devices
42
using error correcting codes (ECC) or parity check
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
409
Read-write (R-W) circuits
Applicants: INTEL CORPORATION[US/US]; Intel Corporation 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors: BAINS, Kuljit; US
NALE, Bill; US
AGARWAL, Rajat; US
Agent: ANDERSON, Vincent; US
FLEMING, Caroline; US
Priority Data:
62/330,33802.05.2016US
Title (EN) INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS
(FR) DÉTECTION ET CORRECTION D'ERREUR (ECC) INTERNE AVEC DES BITS DE SYSTÈME SUPPLÉMENTAIRES
Abstract:
(EN) A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2^N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.
(FR) La présente invention concerne un sous-système de mémoire qui comprend un bus de données pour coupler un dispositif de commande de mémoire à un ou plusieurs dispositifs de mémoire. Le dispositif de commande de mémoire et un ou plusieurs dispositifs de mémoire transfèrent des données pour des opérations d'accès à la mémoire. Le transfert de données comprend le transfert de bits de données et de bits de vérification associés sur une rafale de cycle de transfert. Les dispositifs de mémoire comprennent une détection et une correction d'erreur (ECC pour Error Checking and Correction) interne séparées de la détection et de la correction d'erreur du système gérées par le dispositif de commande de mémoire. Avec un cycle de transfert 2N pour 2^N bits de données pour un dispositif de mémoire, les dispositifs de mémoire peuvent fournir jusqu'à 2N emplacements de mémoire pour N + 1 bits de vérification internes, qui peuvent laisser jusqu'à (2N moins (N + 1)) bits supplémentaires qui doivent être utilisés par le système pour une détection et une correction d'erreur plus solides.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)