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1. (WO2017191943) TEMPLATE FOR GROWING GROUP III-NITRIDE SEMICONDUCTOR LAYER, GROUP III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD THEREFOR
PCT Biblio. Data
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Pub. No.:
WO/2017/191943
International Application No.:
PCT/KR2017/004556
Publication Date:
09.11.2017
International Filing Date:
28.04.2017
IPC:
H01L 23/14
(2006.01),
H01L 21/48
(2006.01),
H01L 23/498
(2006.01),
H01L 33/48
(2010.01),
H01L 21/78
(2006.01),
H01L 23/00
(2006.01),
H01L 33/00
(2010.01),
H01L 33/02
(2010.01),
H01L 33/64
(2010.01)
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
H
ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
64
Heat extraction or cooling elements
Applicants:
AN, Sang Jeong
[KR/KR]; (KR)
Inventors:
AN, Sang Jeong
; (KR)
Priority Data:
10-2016-0054160
02.05.2016
KR
10-2016-0054162
02.05.2016
KR
10-2016-0054575
03.05.2016
KR
Title
(EN)
TEMPLATE FOR GROWING GROUP III-NITRIDE SEMICONDUCTOR LAYER, GROUP III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD THEREFOR
(FR)
MATRICE DE CROISSANCE D'UNE COUCHE SEMI-CONDUCTRICE DE NITRURE DU GROUPE III, DISPOSITIF ÉLECTROLUMINESCENT À SEMI-CONDUCTEURS DE NITRURE DU GROUPE III ET PROCÉDÉS DE FABRICATION ASSOCIÉS
(KO)
3족 질화물 반도체층 성장을 위한 템플릿, 3족 질화물 반도체 발광소자 및 이들을 제조하는 방법
Abstract:
(EN)
Provided are a template for growing a group III-nitride semiconductor layer, a group III-nitride semiconductor light emitting device comprising the same, and manufacturing methods therefor. A template for growing a group III-nitride semiconductor layer comprises: a growth substrate having a first surface, a second surface facing the first surface, and a groove extending from the first surface into the inside thereof; a heat dissipating insert fixedly inserted into the groove; and a nucleation layer formed on the first surface which is partially removed.
(FR)
L'invention se rapporte à une matrice qui permet la croissance d'une couche semi-conductrice de nitrure du groupe III, à un dispositif électroluminescent à semi-conducteurs de nitrure du groupe III comportant ladite couche et à des procédés de fabrication associés. Une matrice qui permet la croissance d'une couche semi-conductrice de nitrure du groupe III comprend : un substrat de croissance ayant une première surface, une seconde surface en regard de la première surface, et une rainure s'étendant depuis la première surface jusqu'à l'intérieur de ladite couche semi-conductrice ; un dispositif de dissipation thermique inséré à demeure dans la rainure ; une couche de nucléation formée sur la première surface qui est partiellement éliminée.
(KO)
3족 질화물 반도체층 성장을 위한 템플릿, 이를 포함하는 3족 질화물 반도체 발광소자 및 이들을 제조하는 방법이 제공된다. 3족 질화물 반도체층 성장을 위한 템플릿은, 제1 면 및 제1 면에 대향하는 제2 면을 가지는 성장 기판으로서, 제1 면으로부터 성장 기판 내부로 뻗어 있는 홈을 구비하는 성장 기판; 홈 내에 삽입되어 고정되는 방열용 인서트(insert); 그리고 일부가 제거된 제1 면 상에 형성되는 씨앗층(nucleation layer)을 포함한다.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language:
Korean (
KO
)
Filing Language:
Korean (
KO
)