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1. (WO2017191706) MEMORY CONTROL CIRCUIT, MEMORY, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM

Pub. No.:    WO/2017/191706    International Application No.:    PCT/JP2017/006642
Publication Date: Fri Nov 10 00:59:59 CET 2017 International Filing Date: Thu Feb 23 00:59:59 CET 2017
IPC: G06F 12/06
G11C 13/00
Applicants: SONY CORPORATION
ソニー株式会社
Inventors: FUJINAMI, Yasushi
藤波 靖
Title: MEMORY CONTROL CIRCUIT, MEMORY, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM
Abstract:
The present invention reduces a necessary buffer capacity in the memory control circuit of a memory having a plurality of memory blocks. The memory control circuit is provided with an interface and a control unit. The interface receives memory access in a prescribed page size to a plurality of memory subblocks. The control unit has a buffer. The control unit divides a process for memory access for each prescribed process size smaller than the page size, and causes each of the plurality of memory subblocks to start the process successively.