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1. (WO2017190643) NOVEL III-V HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/190643 International Application No.: PCT/CN2017/082738
Publication Date: 09.11.2017 International Filing Date: 02.05.2017
IPC:
H01L 29/778 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/205 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
20
including, apart from doping materials or other impurities, only AIIIBV compounds
201
including two or more compounds
205
in different semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants: HANGZHOU DIANZI UNIVERSITY[CN/CN]; 2nd Avenue, Xiasha Higher Education Zone Hangzhou, Zhejiang 310018, CN
Inventors: DONG, Zhihua; CN
CHENG, Zhiqun; CN
LIU, Guohua; CN
KE, Huajie; CN
ZHOU, Tao; CN
Agent: NANJING LI & FENG INTELLECTUAL PROPERTY AGENCY (SPECIAL GENERAL PARTNERSHIP); Wang Feng, Room 1801 Jiangsu International Trade Building No. 50, Zhonghua Road, Qinhuai District Nanjing, Jiangsu 211100, CN
Priority Data:
201610294235.506.05.2016CN
201610297662.906.05.2016CN
201621179373.027.10.2016CN
Title (EN) NOVEL III-V HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
(FR) NOUVEAU TRANSISTOR À EFFET DE CHAMP À HÉTÉROSTRUCTURE III-V
(ZH) 一种新型III-V异质结场效应晶体管
Abstract:
(EN) A III-V heterostructure field effect transistor comprises a substrate material layer (1), a first semiconductor layer (3), a second semiconductor layer (2), a drain electrode (4), a source electrode (5), a gate electrode (8), a first dielectric layer (6) and a second dielectric layer (7), wherein the first semiconductor layer (3) has a larger band gap than the second semiconductor layer (2), and the second semiconductor layer (2) and the first semiconductor layer (3) are combined together to form a heterogeneous structure. A thickness of the first semiconductor layer (3) is not greater than a critical thickness of a two-dimensional electron gas (2DEG) formed in a heterogeneous channel, so that the natural two-dimensional electron gas (2DEG) in the heterogeneous channel is depleted. The III-V heterostructure field effect transistor has the advantages of simple structure, simple preparation process, stable performance, high reliability and the like.
(FR) La présente invention concerne un transistor à effet de champ à hétérostructure III-V qui comprend une couche de matériau de substrat (1), une première couche de semi-conducteur (3), une deuxième couche de semi-conducteur (2), une électrode de drain (4), une électrode de source (5), une électrode de grille (8), une première couche diélectrique (6) et une deuxième couche diélectrique (7), la première couche de semi-conducteur (3) ayant une bande interdite plus grande que la deuxième couche de semi-conducteur (2), et la deuxième couche de semi-conducteur (2) et la première couche de semi-conducteur (3) étant combinées conjointement pour former une structure hétérogène. Une épaisseur de la première couche de semi-conducteur (3) n'est pas supérieure à une épaisseur critique d'un gaz électronique bidimensionnel (2DEG) formé dans un canal hétérogène, de sorte que le gaz électronique bidimensionnel (2DEG) naturel dans le canal hétérogène soit appauvri. Le transistor à effet de champ à hétérostructure III-V présente les avantages d'une structure simple, d'un procédé de préparation simple, de performances stables, d'une fiabilité élevée et similaire.
(ZH) 一种III‐V异质结场效应晶体管,其包括衬底材料层(1),第一半导体层(3)、第二半导体层(2),漏电极(4)、源电极(5)、栅电极(8),第一介质层(6)、第二介质层(7)等;其中第一半导体层(3)具有比第二半导体层(2)更大的禁带宽度,第二半导体层(2)和第一半导体层(3)结合在一起构成异质结构。第一半导体层(3)的厚度不大于在异质沟道中形成二维电子气2DEG的临界厚度,使异质沟道中天然的二维电子气2DEG被耗尽。该III‐V异质结场效应晶体管具有结构简洁,制备工艺简单,性能稳定,可靠性高等优点。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)