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1. (WO2017189124) WAFER LEVEL GATE MODULATION ENHANCED DETECTORS

Pub. No.:    WO/2017/189124    International Application No.:    PCT/US2017/023424
Publication Date: Fri Nov 03 00:59:59 CET 2017 International Filing Date: Wed Mar 22 00:59:59 CET 2017
IPC: G01N 27/414
H01L 31/04
H01L 31/18
H01L 29/772
Applicants: STC. UNM
Inventors: KRISHNA, Sanjay
ZARKESH-HA, Payman
RAMIREZ, David, A.
KLEIN, Brianna
CAVALLO, Francesca
ZAMIRI, Seyedeh, Marziyeh
KAZEMI, Alireza
KADLEC, Clark
Title: WAFER LEVEL GATE MODULATION ENHANCED DETECTORS
Abstract:
A detector or sensor including a transistor having a sensor element that generates a current when exposed to a stimulus such as light or a chemical, in one implementation, the sensor element is positioned between a transistor gate and a transistor channel. When the sensor element is not being exposed to the stimulus, the transistor outputs a first voltage on a transistor drain contact when the transistor Inverts. When the sensor element is being exposed to the stimulus, the transistor outputs a second voltage on the transistor drain contact when the transistor inverts, where the second voltage is higher than the first voltage.