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1. (WO2017188105) TRENCH MOS-TYPE SCHOTTKY DIODE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/188105 International Application No.: PCT/JP2017/015825
Publication Date: 02.11.2017 International Filing Date: 20.04.2017
IPC:
H01L 29/872 (2006.01) ,H01L 29/47 (2006.01) ,H01L 29/861 (2006.01) ,H01L 29/868 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
47
Schottky barrier electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
Applicants: TAMURA CORPORATION[JP/JP]; 1-19-43, Higashi-Oizumi, Nerima-ku, Tokyo 1788511, JP
NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY[JP/JP]; 4-2-1, Nukui-Kitamachi, Koganei-shi, Tokyo 1848795, JP
Inventors: SASAKI, Kohei; JP
HIGASHIWAKI, Masataka; JP
Agent: HIRATA & PARTNERS; 6th Floor, Niban-cho Cashew Building, 4-3, Niban-cho, Chiyoda-ku, Tokyo 1020084, JP
Priority Data:
2016-09127628.04.2016JP
Title (EN) TRENCH MOS-TYPE SCHOTTKY DIODE
(FR) DIODE SCHOTTKY DE TYPE MOS À TRANCHÉE
(JA) トレンチMOS型ショットキーダイオード
Abstract:
(EN) [Problem] To provide a trench MOS-type Schottky diode having a high withstand voltage and low loss. [Solution] According to one embodiment of the present invention, a trench MOS-type Schottky diode 1 is provided, said trench MOS-type Schottky diode having: a first semiconductor layer 10 formed of a Ga2O3 single crystal; a second semiconductor layer 11, which is a layer laminated on the first semiconductor layer 10, and which has a trench 12 opened in a surface 17, said second semiconductor layer being formed of a Ga2O3 single crystal; an anode electrode 13 formed on the surface 17; a cathode electrode 14 formed on the first semiconductor layer 10 surface on the reverse side of the second semiconductor layer 11; and an insulating film 15 covering the inner surface of the trench 12 of the second semiconductor layer 11; and a trench MOS gate 16, which is embedded in the trench 12 of the second semiconductor layer 11 such that the trench MOS gate is covered with the insulating film 15, and which is in contact with the anode electrode 13.
(FR) Le problème décrit par la présente invention est de fournir une diode Schottky de type MOS à tranchée ayant une tension de tenue élevée et une faible perte. Selon un mode de réalisation, la présente invention concerne une diode Schottky de type MOS à tranchée 1, ladite diode Schottky de type MOS à tranchée ayant : une première couche semi-conductrice 10 constituée d'un monocristal de Ga2O3; une seconde couche semi-conductrice 11, qui est une couche stratifiée sur la première couche semi-conductrice 10, et qui a une tranchée 12 ouverte dans une surface 17, ladite seconde couche semi-conductrice étant constituée d'un monocristal de Ga2O3; une électrode d'anode 13 formée sur la surface 17; une électrode de cathode 14 formée sur la surface de la première couche semi-conductrice 10 du côté opposé à la seconde couche semi-conductrice 11; et un film isolant 15 recouvrant la surface interne de la tranchée 12 de la seconde couche semi-conductrice 11; et une grille MOS à tranchée 16, qui est intégrée dans la tranchée 12 de la seconde couche semi-conductrice 11 de telle sorte que la grille MOS à tranchée est recouverte du film isolant 15, et qui est en contact avec l'électrode d'anode 13.
(JA) 【課題】高耐圧かつ低損失のトレンチMOS型ショットキーダイオードを提供する。 【解決手段】一実施の形態として、Ga系単結晶からなる第1の半導体層10と、第1の半導体層10に積層される層であって、面17に開口するトレンチ12を有する、Ga系単結晶からなる第2の半導体層11と、面17上に形成されたアノード電極13と、第1の半導体層10の第2の半導体層11と反対側の面上に形成されたカソード電極14と、第2の半導体層11のトレンチ12の内面を覆う絶縁膜15と、第2の半導体層11のトレンチ12内に絶縁膜15に覆われるように埋め込まれ、アノード電極13に接触するトレンチMOSゲート16と、を有する、トレンチMOS型ショットキーダイオード1を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)