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1. (WO2017185838) THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
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Pub. No.: WO/2017/185838 International Application No.: PCT/CN2017/071705
Publication Date: 02.11.2017 International Filing Date: 19.01.2017
IPC:
H01L 21/77 (2017.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants: BOE TECHNOLOGY GROUP CO., LTD.[CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.[CN/CN]; No.118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors: LI, Liangliang; CN
GUO, Huibin; CN
LIU, Zheng; CN
WANG, Shoukun; CN
FENG, Yuchun; CN
Agent: LIU, SHEN & ASSOCIATES; 10th Floor, Building 1, 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201610279966.228.04.2016CN
Title (EN) THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
(FR) SUBSTRAT DE MATRICE DE TRANSISTORS À COUCHES MINCES ET SON PROCÉDÉ DE PRÉPARATION, ET APPAREIL D'AFFICHAGE
(ZH) 薄膜晶体管阵列基板及其制备方法、显示装置
Abstract:
(EN) A preparation method for a thin film transistor array substrate, comprising: forming, on a base substrate (101), a gate electrode layer (102), a gate insulation layer (103), an oxide semiconductor layer (104), a source and drain electrode layer and a pixel electrode layer. The steps of forming the source and drain electrode layer and forming the pixel electrode layer comprise: successively forming a transparent conductive thin film (106) and a first metal thin film (107) on the oxide semiconductor layer (104), so as to form a laminated layer of the transparent conductive thin film and the first metal thin film, wherein the transparent conductive thin film (106) is in contact with the oxide semiconductor layer (104); and performing one patterning process on the laminated layer of the transparent conductive thin film (106) and the first metal thin film (107) to form a source electrode (1051), a drain electrode (1052) and a pixel electrode (108). The method can save one patterning process, shorten a production time and reduce production costs.
(FR) La présente invention concerne un procédé de préparation d'un substrat de matrice de transistors à couches minces, comprenant : la formation, sur un substrat de base (101), d’une couche d'électrode de grille (102), une couche d'isolation de grille (103), une couche d'oxyde semi-conducteur (104), une couche d'électrode de source et de drain et une couche d'électrode de pixel. Les étapes de formation de la couche d'électrode de source et de drain et de formation de la couche d'électrode de pixel comprennent : la formation successive d'un film mince conducteur transparent (106) et d'un premier film mince métallique (107) sur la couche d’oxyde semi-conducteur (104), de manière à former une couche stratifiée du film mince conducteur transparent et du premier film mince métallique, le film mince conducteur transparent (106) étant en contact avec la couche d’oxyde semi-conducteur (104) ; et la conduite d'un processus de modelage sur la couche stratifiée du film mince conducteur transparent (106) et du premier film mince métallique (107) pour former une électrode de source (1051), une électrode de drain (1052) et une électrode de pixel (108). Le procédé permet d'économiser un processus de modelage, de raccourcir un temps de production et de réduire les coûts de production.
(ZH) 薄膜晶体管阵列基板的制备方法,包括:在衬底基板(101)上形成栅极层(102)、栅绝缘层(103)、氧化物半导体层(104)、源漏电极层和像素电极层。其中,形成源漏电极层和形成像素电极层的步骤包括:在所述氧化物半导体层(104)上依次形成透明导电薄膜(106)和第一金属薄膜(107),以形成所述透明导电薄膜和所述第一金属薄膜的叠层,所述透明导电薄膜(106)与所述氧化物半导体层(104)接触;对所述透明导电薄膜(106)和所述第一金属薄膜(107)的叠层进行一次构图工艺形成源极(1051)、漏极(1052)以及像素电极(108)。该方法可以节省一次构图工艺,缩短生产时间,降低生产成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)