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1. (WO2017184472) PROCESSOR WITH INSTRUCTION LOOKAHEAD ISSUE LOGIC
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Pub. No.: WO/2017/184472 International Application No.: PCT/US2017/027842
Publication Date: 26.10.2017 International Filing Date: 17.04.2017
IPC:
G06F 9/38 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
Applicants: MICROSOFT TECHNOLOGY LICENSING, LLC[US/US]; Attn: Patent Group Docketing (Bldg. 8/1000) One Microsoft Way Redmond, Washington 98052-6399, US
Inventors: SMITH, Burton J.; US
Agent: MINHAS, Sandip; US
CHEN, Wei-Chen Nicholas; US
DRAKOS, Katherine J.; US
KADOURA, Judy M.; US
HOLMES, Danielle J.; US
SWAIN, Cassandra T.; US
WONG, Thomas S.; US
CHOI, Daniel; US
Priority Data:
15/136,12322.04.2016US
Title (EN) PROCESSOR WITH INSTRUCTION LOOKAHEAD ISSUE LOGIC
(FR) PROCESSEUR À LOGIQUE D'ÉMISSION À ANTICIPATION D'INSTRUCTION
Abstract:
(EN) A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.
(FR) La présente concerne un processeur qui possède une mémoire cache d'instructions pour stocker une pluralité d'instructions. Le processeur comprend en outre une logique d'annotation conçue pour déterminer une distance d'anticipation associée à une instruction et annoter ladite ou lesdites mémoires cache d'instructions avec la distance d'anticipation. La distance d'anticipation peut correspondre à un certain nombre d'instructions séparant une instruction qui référence un registre de la définition de registre la plus récente. La distance d'anticipation peut indiquer la distance la plus courte à une instruction ultérieure qui référence un registre que cette instruction définit.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)