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1. (WO2017183574) DOMAIN WALL-UTILIZING SPIN MOSFET AND DOMAIN WALL-UTILIZING ANALOG MEMORY
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Pub. No.: WO/2017/183574 International Application No.: PCT/JP2017/015264
Publication Date: 26.10.2017 International Filing Date: 14.04.2017
IPC:
H01L 29/82 (2006.01) ,G06N 3/06 (2006.01) ,H01L 21/8239 (2006.01) ,H01L 27/105 (2006.01) ,H01L 43/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
82
controllable by variation of the magnetic field applied to the device
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
06
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08
Magnetic-field-controlled resistors
Applicants:
TDK株式会社 TDK CORPORATION [JP/JP]; 東京都港区芝浦三丁目9番1号 3-9-1, Shibaura, Minato-ku, Tokyo 1080023, JP
Inventors:
佐々木 智生 SASAKI Tomoyuki; JP
Agent:
棚井 澄雄 TANAI Sumio; JP
荒 則彦 ARA Norihiko; JP
飯田 雅人 IIDA Masato; JP
荻野 彰広 OGINO Akihiro; JP
Priority Data:
2016-08553121.04.2016JP
Title (EN) DOMAIN WALL-UTILIZING SPIN MOSFET AND DOMAIN WALL-UTILIZING ANALOG MEMORY
(FR) TRANSISTOR MOSFET DE SPIN UTILISANT UNE PAROI DE DOMAINE ET MÉMOIRE ANALOGIQUE UTILISANT UNE PAROI DE DOMAINE
(JA) 磁壁利用型スピンMOSFETおよび磁壁利用型アナログメモリ
Abstract:
(EN) This domain wall-utilizing spin MOSFET (100) is provided with: a domain wall drive layer (1) comprising a domain wall (DW), a first region (1a), a second region (1b), and a third region (1c) positioned between the first region and the second region; a channel layer (5); a magnetization free layer (6) provided on a first end (5aA) on a first surface of the channel layer and arranged so as to contact the third region of the domain wall drive layer; a magnetization fixed layer (7) disposed on the second end (5aB) opposite of the first end; and, disposed between the first end and the second end of the channel layer, a gate electrode (8) provided on the channel layer with a gate insulating layer (9) interposed therebetween.
(FR) Ce transistor MOSFET de spin utilisant une paroi de domaine (100) comporte : une couche de commande de paroi de domaine (1) comprenant une paroi de domaine (DW), une première région (1a), une deuxième région (1b), et une troisième région (1c) positionnée entre la première région et la deuxième région; une couche de canal (5); une couche libre de magnétisation (6) disposée sur une première extrémité (5aA) sur une première surface de la couche de canal et agencée de manière à être en contact avec la troisième région de la couche de commande de paroi de domaine; une couche fixe de magnétisation (7) disposée sur la seconde extrémité (5aB) opposée à la première extrémité; et, disposée entre la première extrémité et la seconde extrémité de la couche de canal, une électrode de grille (8) disposée sur la couche de canal, une couche d'isolation de grille (9) étant intercalée entre celles-ci.
(JA) 磁壁利用型スピンMOSFET(100)は、磁壁(DW)と、第1領域(1a)と、第2領域(1b)と、第1領域および第2領域の間に位置する第3領域(1c)と、を有する磁壁駆動層(1)と、チャネル層(5)と、チャネル層の第1面の第1端部(5aA)に設けられ、磁壁駆動層の第3領域に接するように配置されている磁化自由層(6)と、第1端部の反対の第2端部(5aB)に設けられた磁化固定層(7)と、チャネル層の第1端部及び第2端部の間に、ゲート絶縁層(9)を介して設けられたゲート電極(8)と、を備える。
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African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)