Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2017181698) ARRAY SUBSTRATE, AND DISPLAY DEVICE, AND FABRICATION METHODS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/181698 International Application No.: PCT/CN2016/109460
Publication Date: 26.10.2017 International Filing Date: 12.12.2016
IPC:
H01L 29/786 (2006.01) ,H01L 29/10 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd. Chaoyang District Beijing 100015, CN
Inventors:
LIU, Zheng; CN
LI, Xiaolong; CN
ZUO, Yueping; CN
HUANGFU, Lujiang; CN
Agent:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan Chen 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201610239440.118.04.2016CN
Title (EN) ARRAY SUBSTRATE, AND DISPLAY DEVICE, AND FABRICATION METHODS
(FR) SUBSTRAT DE RÉSEAU, ET DISPOSITIF D'AFFICHAGE ET PROCÉDÉS DE FABRICATION
Abstract:
(EN) A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first electrode, an insulating layer, and a second electrode, over a substrate. A conductive layer is on the insulating layer. A semiconductor layer is on the first electrode, on a first sidewall of the insulating layer, on the conductive layer, on the second sidewall of the insulating layer, and on the second electrode. A first gate electrode is over a portion of the semiconductor layer that is on the first sidewall of the insulating layer. A second gate electrode is over a portion of the semiconductor layer that is on the second sidewall of the insulating layer.
(FR) L'invention concerne un dispositif semiconducteur, un substrat de réseau et un dispositif d'affichage, ainsi que leurs procédés de fabrication. Un exemple de dispositif semiconducteur comprend une première électrode, une couche isolante et une deuxième électrode, sur un substrat. Une couche conductrice se trouve sur la couche isolante. Une couche en semiconducteur se trouve sur la première électrode, sur une première paroi latérale de la couche isolante, sur la couche conductrice, sur la deuxième paroi latérale de la couche isolante et sur la deuxième électrode. Une première électrode de gâchette se trouve sur une portion de la couche en semiconducteur qui se trouve sur la première paroi latérale de la couche isolante. Une deuxième électrode de gâchette se trouve sur une portion de la couche en semiconducteur qui se trouve sur la deuxième paroi latérale de la couche isolante.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)