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1. (WO2017181023) SYSTEMS AND METHODS FOR UNIVERSAL REVERSIBLE COMPUTING
PCT Biblio. Data
Description
Claims
National Phase
Notices
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Pub. No.:
WO/2017/181023
International Application No.:
PCT/US2017/027652
Publication Date:
19.10.2017
International Filing Date:
14.04.2017
IPC:
B82Y 10/00
(2011.01),
G06F 7/53
(2006.01),
G06F 17/00
(2006.01),
G06G 7/32
(2006.01),
H03K 19/20
(2006.01)
B
PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
Y
SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES
10
Nano-technology for information processing, storage or transmission, e.g. quantum computing or single electron logic
G
PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52
Multiplying; Dividing
523
Multiplying only
53
in parallel-parallel fashion, i.e. both operands being entered in parallel
G
PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
G
PHYSICS
06
COMPUTING; CALCULATING; COUNTING
G
ANALOGUE COMPUTERS
7
Devices in which the computing operation is performed by varying electric or magnetic quantities
12
Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor
32
for solving of equations
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
20
characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Applicants:
TRUSTEES OF BOSTON UNIVERSITY
[US/US]; One Silber Way Boston, MA 02215 (US).
THE UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
[US/US]; 12201 Research Parkway, Suite 501 Orlando, FL 32826 (US).
CHAMON, Claudio
[US/US]; (US)
(US only)
.
MUCCIOLO, Eduardo, R.
[US/US]; (US)
(US only)
.
RUCKENSTEIN, Andrei, E.
[US/US]; (US)
(US only)
.
YANG, Zhicheng
[CN/US]; (US)
(US only)
Inventors:
CHAMON, Claudio
; (US).
MUCCIOLO, Eduardo, R.
; (US).
RUCKENSTEIN, Andrei, E.
; (US).
YANG, Zhicheng
; (US)
Agent:
OCHOA, Ricardo
; (US).
SCHURGIN, Stanley, M.
; (US).
MORIARTY, Gordon, R.
; (US).
LEBOVICI, Victor, B.
; (US).
GOUGES D'AGINCOURT, Carolyn
; (US)
Priority Data:
62/323,006
15.04.2016
US
Title
(EN)
SYSTEMS AND METHODS FOR UNIVERSAL REVERSIBLE COMPUTING
(FR)
SYSTÈMES ET PROCÉDÉS DE CALCUL RÉVERSIBLE UNIVERSEL
Abstract:
(EN)
Methods for performing computations using a lattice of interconnected devices are described. The lattice is programmed to perform the computation by choosing a specific logic function for each device. An energy penalty is attributed to each device when the associated input and output bits do not satisfy a truth table of the logic function of the device. Input data is inserted on the boundaries of the lattice by attributing energy penalties to the input and output bits at the boundaries when the states of those bits do not match the input data. The energy in the lattice is lowered for the lattice to reach a configuration where all gate and boundary constraints are satisfied. The result of the computation is read from the output data encoded in the states of the bits of the devices at the boundaries of the lattice which are not already fixed by the input data.
(FR)
L'invention concerne des procédés pour effectuer des calculs à l'aide d'un réseau de dispositifs interconnectés. Le réseau est programmé pour effectuer le calcul en choisissant une fonction logique spécifique pour chaque dispositif. Une pénalité d'énergie est attribuée à chaque dispositif lorsque les bits d'entrée et de sortie associés ne satisfont pas une table de vérité de la fonction logique du dispositif. Des données d'entrée sont insérées sur les limites du réseau en attribuant des pénalités d'énergie aux bits d'entrée et de sortie aux limites lorsque les états de ces bits ne correspondent pas aux données d'entrée. L'énergie dans le réseau est abaissée pour que le réseau atteigne une configuration où toutes les contraintes de grille et de limite sont satisfaites. Le résultat du calcul est lu à partir des données de sortie codées dans les états des bits des dispositifs aux limites du réseau qui ne sont pas déjà fixées par les données d'entrée.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language:
English (
EN
)
Filing Language:
English (
EN
)