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1. WO2017180122 - OPTICAL RECEIVERS

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

Optical Receivers

STATEMENT OF GOVERNMENT I NTEREST

[0001] This invention was made with government support under Contract No. H98230-14-3-001 1 , awarded by the Maryland Procurement Office. The government has certain rights in the invention.

BACKGROUND

[0002] One way that information may be communicated between two devices is by modulating light at one device to form an optical signal and transmitting the optical signal to the other device. One form of modulation that can be used in such optical communication is known as pulse-amplitude modulation (PAM), which, in the context of optical communication, involves modulating the power (intensity) of a light signal so as to encode data for transmission.

[0003] PAM-4 is a form of PAM in which, in the context of optical

communication, there are four different power levels to which the optical signal may be modulated, each corresponding to a different transmission symbol. Each transmission symbol in a PAM-4 optical signal encodes a sequence of two binary bits, such as 00, 01 , 10, and 1 1 .

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Fig. 1 is a conceptual diagram illustrating an example optical receiver.

[0005] Fig. 2 is a conceptual diagram illustrating an example optical receiver front end.

[0006] Figs. 3A-3C are conceptual diagrams illustrating example data slicers, and Fig. 3D is a conceptual diagram illustrating an example edge slicer.

[0007] Fig. 4A is a conceptual diagram illustrating example decoder and CDR logic, Fig. 4B is an example logic table, and Fig. 4C is an example symbol-to-bit sequence correspondence table.

[0008] Fig. 5 is a conceptual diagram illustrating example symbol detection logic.

[0009] Fig. 6A is a conceptual diagram illustrating an example clock generator, and Fig. 6B is a signal diagram illustrating example clock signals.

[0010] Fig. 7 includes example eye diagrams.

[001 1 ] Fig. 8 is a conceptual diagram illustrating an example computing device.

DETAILED DESCRIPTION

[0012] Disclosed herein are examples of optical receivers that are configured to receive a PAM-4 encoded optical signal and convert the received signal into binary data, such as data in a non-return to zero (NRZ) format.

[0013] Throughout this disclosure and in the appended claims, occasionally reference may be made to "a number" of items. Such references to "a number" mean any integer greater than or equal to one. When "a number" is used in this way, the word describing the item(s) may be written with the pluralized "s" for grammatical consistency, but this does not necessarily mean that multiple items are being referred to. Thus, for example, "a number of comparators" could encompass both one comparator and multiple comparators.

[0014] Fig. 1 illustrates an example optical receiver 100. The example optical receiver 100 illustrated in Fig. 1 includes an optical receiver front-end 1 10, a bank of slicers 120, decoder and clock-and-data-recovery (CDR) logic 130, and a clock generator 140.

[0015] The optical receiver front-end 1 10 may include a transimpedance amplifier (TIA) 1 1 1 . The TIA 1 1 1 may receive a photodiode output signal lPD from a photodiode 101 , and may convert the photodiode output signal IPD into a voltage signal VSi9. The photodiode output signal I PD may correspond to a current generated by the photodiode 101 in response to an optical signal received by the photodiode 101 . An example of the optical front-end 1 10 will be discussed in greater detail below with reference to Fig. 2.

[0016] The bank of slicers 120 may include three data slicers (e.g., data slicers 120-1 , 120-2, and 120-3) and at least one edge slicer (e.g., edge slicer 120-4). The data slicers may be for detecting PAM-4 symbols in the received optical signal, while the edge slicer(s) may be for detecting symbol timings in the received optical signal through a clock-and-data recovery (CDR) process.

[0017] In particular, the voltage signal VSi9 output by the TIA 1 1 1 may be input to each of the slicers 120. The slicers 120 may each output N digital signals based on the voltage signal VSi9, where N is an integer greater than 1 . In the example of Fig. 1 , the data slicer 120-1 outputs data signals D ,o - Dh,N-i , the data slicer 120-2 outputs data signals Dm,o - DM,N-i , the data slicer 120-3 outputs data signals Di,o - DI,N-I , and the edge slicer 120-4 outputs edge signals Em,o -

[0018] The slicers 120 may each shift the voltage signal VSi9 based on an offset voltage, thereby generating a shifted voltage signal. The offset voltages set for the slicers 120-1 , 120-2, 120-3, and 120-4 of the example of Fig. 1 are labeled herein AVi , ΔΝ/2, A\fz, and AV4, respectively. Each of the slicers 120, upon shifting the voltage signal VSi9 by the offset amount set for the respective slicer 120, may then determine whether its shifted voltage signal is greater than a threshold voltage VTH and generate a number of comparison signals based on the determination. For example, the comparison signals may be logical 1 when the shifted voltage signal is greater than the threshold voltage VTH, and logical 0 otherwise. Each of the slicers 120 may then generate its respective N digital signals by demuxing the comparison signals. An example of the slicers 120 will be discussed in greater detail below with reference to Figs. 3A-3D.

[0019] The digital signals output by the slicers 120 are input to the decoder and CDR logic 130. The decoder and CDR logic 130 includes logic for detecting and decoding PAM-4 symbols into binary data and logic for a CDR process. In particular, the decoder and CDR logic 130 detects PAM-4 symbols based on the 3N digital signals output by the three data slicers 120-1 , 120-2, and 120-3 (namely, data signals D ,o - Dh,N-i , Dm,o - DM,N-i , and Di,o - DI,N-I), and decodes the detected PAM-4 symbols into binary data DOUT. The decoder and

CDR logic 130 may also use at least the N digital signals output by the edge slicer 120-4 (namely, edge signals Em,o - EM,N-i ) for edge detection in the CDR process. An example of the decoder and CDR logic 130 will be discussed in greater detail below with respect to Figs. 4A-4C.

[0020] The clock generator 140 may generate clock signals for use by the slicers 120. For example, in the example optical receiver shown in Fig. 1 , the clock generator 140 generates a clock Cl-Κφο that has a frequency that is half of a symbol rate of the received optical signal. In this example, the optical receiver also generates a clock ΰΙ-Κφθο that has the same frequency as the clock Cl-Κφο and a 90 degree phase difference from the clock Cl-Κφο, a clock ΰΙ_Κφΐ 8ο that has the same frequency as the clock Cl-Κφο and a 180 degree phase difference from the clock Cl-Κφο, and a clock ΰΙ_Κφ27ο that has the same frequency as the clock Cl-Κφο and a 270 degree phase difference from the clock Cl-Κφο. An example of the clock generator 140 will be discussed in greater detail below with respect to Fig. 6.

[0021] In the example optical receiver 100 of Fig. 1 , the data slicers 120-1 , 120-2, and 120-3 may each generate their N digital signals based on the clock signals Cl-Κφο and ΰΙ_Κφΐ 8ο, while the edge slicer 120-4 may generate its N digital signals based on clock signals ΰΙ-Κφθο and ΰΙ_Κφ27ο. A control signal CTRLCDR that is generated by the decoder and CDR logic 130 as part of a CDR process is input to the clock generator 140 to control the clock generator 140. For example, the control signal CTRLCDR may control phases of the clocks

Cl-Κφο, ΰΙ_Κφ9ο, ΰΙ_Κφΐ 8ο, ΰΙ_Κφ27ο such that the data slicers 120-1 , 120-2, and 120-3 sample VSi9 at timings corresponding to symbols in the signal represented by Vsig (hereinafter "symbol timings").

[0022] In the example optical receiver 100 of Fig. 1 , the offset voltages may be set such that AVi > Δ\/2 > ΔΝ/3. Thus, in the example optical receiver 100, AVi may be considered a high offset, ΔΝ/2 may be considered a middle offset, and ΔΝ/3 may be considered a low offset. The indices h, m, and / are used herein to indicate a correspondence to the high offset (e.g., AVi), the middle offset (e.g., AV2), and the low offset (e.g., ΔΝ ), respectively. Thus, in the example of Fig. 1 , the N digital signals output by the data slicer 120-1 are labeled D ,o - Dh,N-i , since the data slicer 120-1 uses the high offset AVi . Similarly, the digital signals output by the data slicer 120-2 are labeled Dm,o - DM,N-i since they are based on the middle offset ΔΝ/2, and the digital signals output by the data slicer 120-3 are labeled Di,o - DI,N-I since they are based on the low offset ΔΝ/3. Furthermore, the shifted voltage signal in the data slicer 120-1 is designated V* , the shifted voltage signal in the data slicer 120-2 is designated V*m, the shifted voltage signal in the data slicer 120-3 is designated V* , and the shifted voltage signal in the edge slicer 120-4 is designated V*m.

[0023] In the example optical receiver 1 00 of Fig. 1 , the offset voltages may be set such that AV4 = ΔΝ/2. Thus, in Fig. 1 the digital signals output by the edge slicer 120-4 are labeled Em,o - EM,N-i , since they are based on the middle offset AV4 = ΔΝ/2. However, in other examples the offset voltage AV4 of the edge slicer 120-4 may be set to equal a voltage other than ΔΝ/2, such as one of the offset voltages AVi or ΔΝ/3 or some other voltage.

[0024] In certain examples, each of the offset voltages AV may be based on a common mode voltage Vcm of the voltage signal VSi9. For example, the optical receiver front-end 1 1 0 may determine the common mode voltage Vcm of the voltage signal VSi9, and may output Vcm to a subsequent stage for generation of the offset voltages A based on Vcm. For example, the offset voltage AVi may equal VCM + VA, the offset voltage ΔΝ/2 may equal VCM, and the offset voltage ΔΝ/3 may equal Vcm - VB, where VA and VB are specific voltages. Values of VA and VB may be set, for example, such that: (a) the data slicer 120-1 outputs a logic-high value when the voltage signal VSi9 encodes a high PAM-4 symbol and a logic-low otherwise, and (b) the data slicer 120-3 outputs a logic-low when the voltage signal VSi9 encodes a low PAM-4 symbol and a logic-high otherwise. Values for VA and VB may be determined, for example, by experiment. For example, an iterative process may be used to converge on a value of VA that minimizes a bit error rate (BER) of the optical receiver. For example, a signal encoding a training pattern may be repeatedly input to the optical receiver 1 00 while varying the value set for VA (for example, using a digital-to-analog converter) and measuring the BER each iteration, whereby a value for VA that

minimizes the BER may be found. In some examples, VB may be automatically set so as to be equal to VA. In other examples, an optimal value for VB may be determined by the same process described above with respect to VA. The combining of the offset voltage VCM with the voltages VA or VB to obtain the offset voltages A may be performed, for example, by a voltage summing circuit (not illustrated), which may be included within the slicers 120 or external to the slicers 120.

[0025] As described above, the slicers 120 may determine whether their respective shifted voltage signals V* are greater than a threshold voltage VTH. This determination may be made by performing a comparison between the respective shifted voltage signals V* and some other voltage value, which could be a time-varying signal value or a fixed value. In certain examples, the slicers 120 may each compare their corresponding shifted voltage signal V* to its complementary signal V*, which may indicate whether the shifted voltage signal V* is greater than a threshold voltage VTH. In this case, the threshold voltage VTH may be equal to a common DC level of the shifted voltage signals V* and its complementary signal V*, or in other words VTH may equal the value of V* for which V* - V* = 0. In other examples, the shifted voltage signal V* may be compared directly to a fixed voltage value (i.e., the threshold voltage VTH) to determine whether the shifted voltage signal V* is greater than the threshold voltage VTH. In this case, the fixed voltage value may be set so as to

approximate a DC level of the shifted voltage signal V*.

[0026] In certain examples, the slicers 120 may each generate their N digital signals by demuxing a number of comparison signals that are generated by determining whether the shifted voltages signal V* is greater than the threshold voltage VTH. For example, each of the slicers 120 may include a number of demux stages that demux the comparison signals into the N digital signals.

[0027] Thus, the example optical receiver 100 may receive a PAM-4 encoded optical signal and convert the optical signal to an electronic signal, detect the PAM-4 symbols in the signal, and decode the PAM-4 symbols into binary data.

[0028] The optical front end 1 10 may achieve high gain and low noise by using the TIA 1 1 1 , which allows for higher sensitivity than might otherwise be achievable.

[0029] The use of the level shifting amplifier 121 in the slicers 120 may allow for even further increased gain of the signal. The use of the level shifting amplifier 121 may also reduce the capacitive load on the TIA 1 1 1 , which may help increase a bandwidth of the TIA 1 1 1 . The use of the level shifting amplifier 121 may also allow the slicer 120 to have a larger offset range than might otherwise be achievable.

[0030] The slicers 120 are able to split the incoming symbols of the received signal into N data streams, thereby allowing for parallel processing of the received symbols in the decoder and CDR logic 130. This may provide additional time for the decoder and CDR logic 130 to process each received symbol, which may be helpful when the symbol rate of the received optical symbol is sufficiently high that serial processing of the received symbols becomes difficult or impossible.

[0031] For example, if the symbol rate of the received signal is 32 GBd, components of the decoder and CDR logic 130 might need to be expensive, be complex, and/or take up a large amount of space in order to serially process the received symbols at this high symbol rate. However, in this example, the N data streams output by each of the slicers 120 would each have a symbol rate of 32/N GBd, and the decoder and CDR logic 130 may be able to process these streams in parallel with components that are comparatively less expensive, are comparatively less complex, and/or take up comparatively less space. For example, if N = 32, then the symbol rate of each data stream output by the slicers 120 would be 1 GBd, which may be more manageable for the decoder and CDR logic 130.

[0032] In particular, certain examples of the optical receiver 100 are capable of providing a communication rate of at least 64Gb/s at 16nm FinFET process, while maintaining a bit error rate (BER) of 10"12.

[0033] Fig. 2 illustrates an example optical receiver front-end 1 10. As described above, the optical receiver front-end 1 10 includes a TIA 1 1 1 . The optical receiver front-end 1 1 0 may also include a low-dropout regulator (LDO) 1 12, automatic gain control (AGC) circuitry 1 13, and DC offset voltage control (DCOC) circuitry 1 14.

[0034] The TIA 1 1 1 may be formed, for example, from three inverter stages (not illustrated) with resistive feedback (not illustrated) in the first and third stages. The resistive feedback of the third stage may be, for example, able to change its resistance based on a control signal from the AGC 1 13; for example, the feedback resistance may include a transistor connected in parallel to a resistor.

[0035] The LDO 1 12 provides a constant voltage power supply to the TIA 1 1 1 .

[0036] The AGC circuitry 1 13 automatically controls a gain of the TIA 1 1 1 . For example, the AGC circuitry 1 13 may automatically reduce a gain of the TIA when the photodiode output signal IPD is large (which may happen when the power of the received optical signal is high), thus keeping the voltage signal VSi9 within a particular range that may facilitate normal operation of the slicers 120. For example, the AGC circuitry 1 13 may monitor the signal VSi9, and may control the gain of the TIA 1 1 1 based on VSi9. The AGC circuitry 1 13 may control the gain of the TIA 1 1 1 by generating a signal that controls a feedback resistance within the TIA 1 1 1 . For example, the AGC circuitry 1 13 may determine whether Vsig exceeds Vcm (which may be obtained from the DCOC circuitry 1 14) by more than a certain amount, and if so the ADC circuity 1 13 may send a control signal to the TIA 1 1 1 that reduces a feedback resistance in the TIA 1 1 1 , thus reducing the gain of the TIA 1 1 1 . For example, when the resistive feedback of the third stage includes a transistor connected in parallel to a resistor, the control signal may decrease the resistance of the resistive feedback by turning on the transistor.

[0037] The DCOC circuitry 1 14 may cancel a DC voltage offset of the TIA 1 1 1 that is due to a DC component of the photodiode output signal IPD. In addition, the DCOC circuitry 1 14 may obtain the common mode voltage Vcm of the

voltage signal VSi9, which may be output to the slicers 120 for use in generating the offset voltages
For example, the DCOC circuitry 1 14 may include a low-pass filter that receives the output of the TIA 1 1 1 and outputs Vcm. The DCOC circuitry 1 14 may then, based on Vcm, subtract from an input node of the TIA 1 1 1 a portion of current that corresponds to the aforementioned DC component of IPD.

[0038] Figs. 3A-3D illustrate example slicers 120. Figs. 3A-3C illustrate example data slicers 120-1 , 120-2, and 120-3, while Fig. 3D illustrates an example edge slicer 120-4.

[0039] The example data slicer 120-1 illustrated in Fig. 3A includes a voltage shifting amplifier 121 , and a comparison section 122.

[0040] The voltage shifting amplifier 121 shifts the voltage signal VSi9 based on the offset voltage AVi , and outputs a shifted voltage signal V . In the example data slicer 120-1 , the voltage shifting amplifier 121 may also output the signal ν , which is the complementary signal of the shifted voltage signal V . The voltage shifting amplifier 121 may be, for example, a CML-buffer.

[0041] The comparison section 122 determines whether the shifted voltage signal V is greater than a threshold voltage VTH, generates comparison signals based on the determination, and generates N digital signals D ,o - Dh,N-i by demuxing the comparison signals. The determinations may be performed at timings controlled by input clock signals(s) so as to coincide with symbol timings in the received signal. The comparison signal for a given symbol timing S, indicates whether the shifted voltage signal V is greater than the threshold VTH at the given symbol timing S,. This information, when combined with similar information from the other slicers 120, may be used by the decoder and CDR logic 130 to determine which PAM-4 symbol is represented in the voltage signal Vsig at the given symbol timing S,.

[0042] For example, the comparison section 122 may include a number of comparators 124 that each compare the shifted voltage signal V with another voltage to determine whether the shifted voltage signal V is greater than the threshold voltage VTH. In the example illustrated in Fig. 3A, the comparators 124 perform the aforementioned determination by comparing the shifted voltage signal V with its complementary signal V . In this example, an output of one of the comparators 124 is a logical high value whenever the shifted voltage signal is greater than its complementary signal ν , and a logical low value whenever the shifted voltage signal V is less than its complementary signal ν . As described above, this comparison indicates whether the voltage signal V is greater than a threshold voltage VTH that may be equal to a common DC level of the signals V and V . Thus, the outputs of the comparators 124 are examples of the comparison signals described above. The output of a given comparator 124 for a given symbol timing S, indicates whether the shifted voltage signal V is greater than the threshold VTH at the symbol timing S,. The comparators 124 may correct for a DC offset thereof based on DC offset cancelation signal input thereto, which may be generated by DC offset cancellation circuitry (not illustrated).

[0043] The comparators 124 may be clocked comparators that perform the comparisons at specific timings based on an input clock signal. In particular, the comparators 124 within the data slicer 120-1 may be controlled by different clock signals that are configured such that the comparators 124 compare the shifted voltage signal V and the signal ν at different timings. In addition, the clock signals may be such that the comparators 124 within the data slicer 120-1 compare the shifted voltage signal V and the signal ν at symbol timings, such that at each symbol timing one of the comparators is performing the comparison and the comparators 124 cyclically alternate which comparator 124 is performing the comparison.

[0044] For example, in Fig. 3A the clock Cl-Κφο controls the comparator 124-2 and the clock CLKc iso controls the comparator 124-1 . The clocks CL-Κφο and ΰΙ_Κφΐ 8ο each have a frequency that is half of the symbol rate of the signal received by the optical receiver 100, and their phases are set such that the comparators 124-1 and 124-2 will alternately compare the signals V and V at every-other symbol timing. For example, see the clock signals illustrated in Fig. 6B. Thus, for example, the comparator 124-2 may perform the comparison at symbol timings So, S2, S4, ... , while the comparator 124-1 may perform the comparison at symbol timings Si , S3, S5, .... The data slicer 120-1 may include a clock converter 125 that receives the clock signals from the clock generating section 140 in one format and converts the clock signals into another format for use by the comparators 124. For example, the clock signals output by the clock generating section may be in common-mode logic (CM L) format, and the clock converter 125 may convert the clock signals into complementary metal-oxide-semiconductor (CMOS) format.

[0045] The comparison section 122 may also include a number of demux stages 123. Because the comparators 124-1 and 124-2 generate two comparison signals from one shifted voltage signal V (one comparison signal for odd symbol timings and one comparison signal for even symbol timings), the comparators 124-1 and 124-2 can be said to perform a demuxing function in addition to their comparison function. Thus, the comparators 124-1 and 124-2 may be considered as a first demux stage 123-1 out of the number of demux stages 123, wherein the first demux stage 123-1 has a demux ratio of 1 :2. Additional demux stages (if any), such as demux stages 123-2 through 123-p in Fig. 3A, may be formed from any type of demuxers, such as D-Flip-Flop demuxers.

[0046] Any number of demux stages 123 may be included in the comparison section 122, in order to obtain the N digital signals D ,o - Dh,N-i . Using demuxers with lower demux ratios may result in using more demux stages 123 to obtain the N digital signals D ,o - Dh,N-i , while using demuxers with higher demux ratios may result in using fewer demux stages 123. However, demuxers with higher demux ratios may be more expensive or complicated than demuxers with lower demux ratios, or may not be able to operate at a desired speed. In certain examples, earlier demux stages 123 may have lower demux ratios than subsequent demux stages 123, since the earliest demux stages 123 may need to operate at the highest speeds.

[0047] For example, if N = 32, then one possible arrangement of the demux section 122 may include a first demux stage 123-1 with a 1 :2 demux ratio (which may be formed by the comparators 124-1 and 124-2), a second demux stage 123-2 with two 1 :4 demuxers (one for each of outputs of the first demux stage), and a third demux stage 123-3 with eight 1 :4 demuxers (one for each of outputs of the second demux stage).

[0048] When more than one demux stages 123 are provided, a clock divider 126 may be included in the slicer 120 to generate clock signals for the demux stages 123-2 through 123-p based on the clock signals output by the clock converter 125. The clock divider 126 may generate clocks for a given demux stage 123-/ based on the clocks of a previous demux stage 123-(i-1 ).

[0049] Fig. 3B illustrates an example of the data slicer 120-2. The data slicer 120-2 includes similar components as those of the data slicer 120-1 described above, and duplicative description thereof is omitted.

[0050] The data slicer 120-2 differs from the data slicer 120-1 in that the offset voltage that is set for the data slicer 120-2 is AV2 (rather than AVi). As a result, the shifted voltage signal in the data slicer 120-2 is V (rather than V ). Thus, the N digital signals output by the data slicer 120-2 are labeled Dm,o - DM,N-i .

[0051] Fig. 3C illustrates an example of the data slicer 120-3. The data slicer 120-3 includes similar components as those of the data slicer 120-1 described above, and duplicative description thereof is omitted.

[0052] The data slicer 120-3 differs from the data slicer 120-1 in that the offset voltage that is set for the data slicer 120-3 is ΔΝ/3 (rather than AVi). As a result, the shifted voltage signal in the data slicer 120-3 is V (rather than V ). Thus, the N digital signals output by the data slicer 120-3 are labeled Di,o - DI,N-I .

[0053] Fig. 3D illustrates an example of the edge slicer 120-4. The edge slicer 120-4 includes similar components as those of the data slicer 120-1 described above, and duplicative description thereof is omitted.

[0054] The edge slicer 120-4 differs from the data slicers 120-1 , 120-2, and 120-3 in that the offset voltage that is set for the edge slicer 120-4 is AV4. As a result, the shifted voltage signal in the edge slicer 120-4 is V*. The value of the offset voltage AV4 may be flexibly selected so as to equal, for example, one of the offset voltages AVi , ΔΝ/2, and ΔΝ/3. In examples in which AV4 = ΔΝ/2, then V* = V^, and in this case the transition edges in a middle eye region of the received optical signal may be used as edge information for the decoder and CDR logic 130. In examples in which AV4 = AVi , then V* = V^, and in this case the transition edges in a high eye region of the received optical signal may be used as edge information for the decoder and CDR logic 130. In examples in which AV4 = ΔΝ/3, then Ve* = ½*, and the transition edges in a low eye region of the received optical signal may be used as edge information for the decoder and CDR logic 130. In certain examples the value of the offset voltage AV4 may be changed occasionally during operation so as to alternate between the various eye regions for sampling transition edges.

[0055] The edge slicer 120-4 further differs from the data slicer 120-1 in that the comparators 124 of the edge slicer 120-4 are controlled by clock signals that are phase shifted relative to the clock signals that control the data slicers 120-1 through 120-3. The phase shifts are such that the edge slicer 120-4 performs comparisons at timings in-between the symbol timings. Thus, the N digital signals output by the edge slicer 120-4 may be referred to as edge signals, and hence are labeled in Fig. 3D as Em,o - Em,N-i . Figure 6B illustrates examples of such clock signals.

[0056] For example, when the clocks Cl-Κφο, and CLKctnso are used to control the comparators 124 of the data slicers, then the clocks ΰΙ_Κφ90, and CLKc^o may be used to control the comparators 124 of the edge slicer 120-4, as illustrated in Fig. 3D. As can be seen in Fig. 6B, these clock signals may result in the comparators 124 performing their comparisons at transition timings in-between symbol timings.

[0057] In certain examples, all of the slicers 120 may have the same internal structure as one another, with differences between the slicers 120 being found in the offset voltages AV, that are set for the respective slicers 120 and in the clock signals that are used in the slicers 120.

[0058] Although one edge slicer is illustrated in Fig. 1 (namely, edge slicer 120-4), multiple edge slicers could be included in the optical receiver 100. In such a case, the edge slicers may have different offset voltages from one another. For example, one edge slicer may be set to the middle offset, one edge slicer may be set to the high offset, and one edge slicer may be set to the low offset.

[0059] Although Figs. 3A-3D illustrate two comparators 124 per slicer 120, any number of comparators 124 could be included in each of the slicers 120. In general, if there are X comparators 124 included in each slicer 120, where X > 1 , then there may be X clock(s) for controlling the X comparators 124 of any given slicer 120. In such a case, each of the X clocks for a given slicer 120 may have a frequency that is 1 /X times the symbol rate of the received signal. When there are multiple comparators 124 in each slicer 120 (e.g., when X > 1 ), then the X clocks for any given slicer 120 may be phase-shifted from one another by increments of 360/X degrees. The data slicers (e.g., data slicers 120-1 through 120-3) may all use the same clocks as one another, while the edge slicer(s) (e.g., edge slicer 120-4) may use clocks that are phase shifted 180/X degrees from the clocks used for the data slicers. Thus, the clock generator 140 may generate a 2X-phase clock (i.e., 2X clock signals with the same frequency and different phases) for the bank of slicers 120 (i.e., X clocks for the data slicers and X clocks for the edge slicers). This means that, in certain examples, a maximum number of comparators 124 per slicer 120 may be related to the ability of the clock generator 140 to generate a sufficient number of clocks within acceptable operation parameters.

[0060] For example, if there are four comparators 124 in each of the slicers 120 (i.e., X = 4), then the data slicers 120-1 through 120-3 may be controlled using clocks having phases φο, ΦΘΟ, φι βο, and Φ2 0, while the edge slicer 120-4 may be controlled using clocks having phases φ45, Φ135, Φ225, and Φ315, with all of the aforementioned clocks having a frequency that is 1 /4 the symbol rate. [0061 ] When multiple comparators 124 are included in each of the slicers 120 (i.e. , when X >1 ), then the comparators 124 may be considered as a first demux stage 123-1 , with a demux ratio of 1 :X.

[0062] When exactly one comparator 124 is included in each of the slicers 120 (i.e. , when X = 1 ), then the comparator 124 would not necessarily be part of any of the demux stages 123. In such an example, a first demux stage 123-1 may be provided downstream of the comparator 124. In such an example, a single clock signal may control the comparator 124 which may have a frequency equal to the symbol rate, and the clock signal for the edge slicer may be phase shifted 180 degrees from the clock signal for the data slicers.

[0063] Although the comparators 124 shown in Figs. 3A-3D determine whether the shifted voltage signal V is greater than the threshold voltage VTH by comparing the shifted voltage signal V with its complementary signal ν , the determination could be made in other ways. For example, the comparators 124 could compare the shifted voltage signal V directly to a voltage value that corresponds to the threshold voltage VTH.

[0064] Fig. 4A illustrates an example of the decoder and CDR logic 1 30. The example decoder and CDR logic 130 may include PAM-4 symbol detector logic 131 , PAM-4 to binary decoder logic 1 32, and CDR logic 133.

[0065] The PAM-4 symbol detector logic 131 may receive 3N digital signals from the data slicers 120-1 through 120-3, and based on these signals may detect PAM-4 symbols of the received optical signal according to the logic table shown in Fig. 4B. The four levels of the PAM-4 encoding are labeled herein for convenience Ή" (i.e. , high), "MH" (i.e. , middle-high), "ML" (i.e. , middle-low), and "L" (i.e. , low), in descending order of magnitude. Fig. 7 illustrates graphically the PAM-4 symbol levels.

[0066] The PAM-4 symbol detector logic 131 may be any logic that

implements the logic table shown in Fig. 4B. In particular, for a given symbol timing S,, the detected symbol may be determined based on the digital signals D ,i, Dm,i, and Dij. If the digital signal Dh,i is logical 1 , then the PAM-4 symbol that is detected is an H symbol (regardless of the values of the digital signals Dm,i and Dij). If the digital signal D j is logical 0 and the digital signal Dm,i is logical 1 , then the PAM-4 symbol that is detected is an MH symbol (regardless of the value of the digital signal DIJ). If the digital signal DIJ is logical 1 and the digital signal Dm,i is logical 0, then the PAM-4 symbol that is detected is an ML symbol (regardless of the value of the digital signal Dhj). If the digital signal DIJ is logical 0, then the PAM-4 symbol that is detected is an L symbol (regardless of the values of the digital signals D j and Dm,i). A signal indicating which PAM-4 symbol has been detected for the given symbol timing S, may be sent to the PAM-4 to binary decoder logic 1 32. An example of PAM-4 symbol detector logic 1 31 is shown in Fig. 5.

[0067] The PAM-4 to binary decoder logic 1 32 may be any logic that converts the detected PAM-4 symbols into the appropriate binary bit sequences. The correspondence between bit sequences and PAM-4 symbol may be arbitrarily determined by a communication protocol being used. For example, Fig. 4C illustrates one possible set of correspondences between PAM-4 symbols and binary bit sequences. The PAM-4 to binary decoder logic 1 32 may output a data stream DOUT composed of the binary bits sequences obtained from decoding the detected PAM-4 symbols. Thus, for example, if a first symbol So is an H, a second symbol Si is an L, and a third symbol S2 is an MH, then the corresponding data stream DOUT may be 1 1 001 0, output in the order of left to right.

[0068] The bit-rate of the data stream DOUT may be twice the symbol rate of the optical signal, as each PAM-4 symbol encodes two bits. The data stream DOUT may be in any binary format, such as a non-return to zero (NRZ) format. The data stream DOUT may be subjected to subsequent stages of processing, such as gray decoding and forward error correction (FEC) processing.

[0069] The CDR logic 1 33 may be any logic that performs CDR processing based on the digital signals output by the slicers 120. For example, the CDR logic 1 33 may include edge detection logic that detects edges of symbol timings in the received signal based at least on the edge signals Em,o - EM,N-i . The CDR logic 1 33 may output a control signal CTR LCDR, which may control the clock

generator 140 to adjust the phases of the clock signals such that the

comparators 1 24 perform their comparisons during symbol timings. The CDR logic 1 33 may also use the data signals output by the data slicers 120-1 through 120-3 in the CDR process, in addition to the edge signals output by the edge slicer 120-4.

[0070] Fig. 5 illustrates an example of the PAM-4 symbol detector logic 1 31 . The example PAM-4 symbol detector logic 1 31 includes N sets of four AN D logic gates 500, with each set of four logic gates 500 corresponding to a different symbol timing S,. For example, a first set of AN D logic gates 500, which corresponds to the 0TH symbol timing So, receives the signals D ,o, Dm,o, and Di,o, and detects a PAM-4 signal for the 0TH symbol timing So based on these signals. The PAM-4 symbol detector logic 1 31 may indicate the identity of the detected PAM-4 symbol for a given symbol timing S, by driving a wiring corresponding to the detected signal to a logical high value (e.g., the Ho wiring may be pulsed high when the detected symbol for the 0TH symbol timing So is H).

[0071] The example PAM-4 symbol detector logic 1 31 illustrated in Fig. 5 is merely one possible logic that implements the logic table shown in Fig. 4B, and any other logic could be used that implements the logic table shown in Fig. 4B. For example, OR gates, NOR gates, NAN D gates, XOR gates, and/or XNOR gates could be used instead of (or in addition to) AN D gates.

[0072] Fig. 6A illustrates an example of the clock generator 140. The example clock generator 140 may include a phase-locked-loop (PLL) 140, a phase interpolator 140, and clock distribution circuitry 143.

[0073] The PLL 141 may receive a reference frequency fref and generate a multiple-phase clock based thereon. The multiple-phase clock may consist of M clock signals with the same frequency as one another and different phases, where M is a positive integer. The phases of the M clock signals may be separated by 360/M degrees from one another. For example, in Fig. 6A the multiple-phase clock generated by the PLL 141 includes the signals ΟίΚφΑ, CLKC))A+9O, CLKC))A+I 8O, and CLKC))A+27O. The frequency of the multiple-phase clock may be k times the reference frequency fref, where k can be an integer or fractional number greater than zero.

[0074] The phase interpolator 142 may shift a phase of each of the clock signals that is output by the PLL 141 by a programmable phase shift <9Φ. The phase shift <¾ may be negative or positive, and may be variably controlled based on the control signal CTRLCDR. For example, in Fig. 6A the phase interpolator 142 outputs a multiple-phase clock that includes the clock signals Cl-Κφο, ΟΙ_Κφ9ο, ΟΙ_Κφΐ8ο, and ΟΙ_Κφ27ο, where: the phase of Cl-Κφο is equal to the phase of CI-ΚΦΑ shifted by <¾ (i.e., φο = ΦΑ + 3φ), the phase of ΟΙ_Κφ9ο is equal to the phase of ΟΙ_ΚΦΑ+9Ο shifted by <¾ (i.e., ΦΘΟ = ΦΑ + 90+ <¾), and so on.

[0075] For example, consider the signals illustrated in Fig. 6B. An example voltage signal VSi9 is illustrated, with symbol timings indicated by the notation S,. A symbol timing S, may correspond to, for example, a period of time in which the received signal stabilizes at a symbol level. The symbol timings are separated from one another by transition periods in which the received signal may change from one symbol level to another symbol level. In the example of Fig. 6B, the signals CL-Κφο and ΟΙ_Κφΐ8ο each correspond to every-other symbol timing S,, thus causing the comparators 124 in the data slicers 120-1 through 120-3 to perform their comparisons at the symbol timings S, (with the comparators 124-1 and 124-2 alternating back and forth every-other symbol timing S,). In the example of Fig. 6B, the signals ΟΙ_Κφ9ο and ΟΙ_Κφ27ο each correspond to every-other transition period, and thus cause the comparators 124 in the edge slicer 120-4 to perform their comparisons during the transition periods (with the comparators 124-1 and 124-2 alternating back and forth every-other transition period).

[0076] The clock distribution circuitry 143 may distribute the clock signals to the slicers 120. For example, the clock distribution circuitry 143 may include buffers, wiring lines, delay elements, and the like that are configured to ensure that corresponding clock signals that arrive at different devices are properly synchronized. For example, the clock distribution circuitry 143 may be

configured to ensure that the signal CL-Κφο that is received at the slicer 120-1 is properly synchronized with the signal CL-Κφο that is received at the slicer 120-3.

[0077] Fig. 7 illustrates example eye diagrams for the example optical receiver 100. The eye diagrams are simulated based on a 400uA input current or equivalent 570uW optical input power, an optical signal having a symbol rate of 32 GBd, and the optical receiver 100 being formed using 16nm FinFET process.

[0078] A top left eye diagram illustrates an output of a Mach-Zehnder modulator (MZM) of an optical transmitter transmitting an optical signal to the optical receiver 100. The PAM-4 symbol levels H, MH, ML, and L are illustrated.

[0079] The top right eye diagram illustrates the voltage signal VSi9 that is output by the TIA 1 1 1 based on the optical signal.

[0080] The bottom left eye diagram illustrates the difference between the shifted voltage V of the data slicer 120-1 and its complementary signal ν . As can be seen in the diagram, the signal has been shifted by the voltage shifting amplifier 121 based on the high offset AVi so that a value of 0V (shown by the dashed line) is approximately centered within the top eye of the eye diagram. Thus, if the symbol of the signal at the time that the comparators 124 perform their comparison is an H symbol, then V - ν > 0 and the comparators 124 of the data slicer 120-1 will output logical 1 , and if the symbol is anything other than H then < 0 and the comparators 124 of the data slicer 120-1 will output logical 0.

[0081] The bottom center eye diagram illustrates the difference between the shifted voltage V of the data slicer 120-2 and its complementary signal V . As can be seen in the diagram, the signal has been shifted by the voltage shifting amplifier 121 based on the middle offset ΔΝ/2 so that a value 0V (shown by the dashed line) is approximately centered within the middle eye of the eye diagram. Thus, if the symbol of the signal at the time that the comparators 124 perform their comparison is an H symbol or an MH symbol, then V - > 0

and the comparators 124 of the data slicer 120-2 will output logical 1 , and if the symbol is an ML symbol or an L symbol then V^ - V^ O and the comparators 124 of the data slicer 120-2 will output logical 0.

[0082] The bottom right eye diagram illustrates the difference between the shifted voltage V of the data slicer 120-3 and its complementary signal Vf . As can be seen in the diagram, the signal has been shifted by the voltage shifting amplifier 121 based on the low offset ΔΝ/3 so that a value 0V (shown by the dashed line) is approximately centered within the lower eye of the eye diagram. Thus, if the symbol of the signal at the time that the comparators 124 perform their comparison is an L symbol, then V - < 0 and the comparators 124 of the data slicer 120-3 will output logical 0, and if the symbol is anything other than L then - Vf > 0 and the comparators 124 of the data slicer 120-3 will output logical 1 .

[0083] Fig. 7 illustrates wide open PAM-4 eye-diagrams at a symbol rate of 32 GBd (bit rate of 64Gb/s). These wide-opened eye-diagrams indicate a healthy optical transceiver link which is able to support a BER of 10"12 at a bit rate of 64Gb/s.

[0084] Fig. 8 illustrates an example of a computing device 800. The computing device 800 may include processing circuitry 810, an optical transmitter 820, an optical transmission medium 830, an optical receiver 840, and a memory device 850. The computing device 800 may generate data D that is to be transmitted to the memory device 850. The optical transmitter 820 may generate an optical signal LD by encoding the data D using PAM-4 encoding, and transmit the optical signal LD via the optical medium 830. The optical receiver 840 may receive the optical signal LD, decode the signal from PAM-4 into binary data D' , and output the data D' to the memory device. If there are no bit errors in the communication, then the data D' will be the same as the data D. Additional processes may be performed by the optical transmitter 820 and the optical receiver 840 as part of the various conversions between the data D, the optical signal LD, and the data D' , such as gray code processing and forward error correction (FEC) processing.

[0085] The processing circuitry 810 may be any circuitry capable of executing machine-readable instructions, such as a central processing unit (CPU), a microprocessor, a microcontroller device, a digital signal processor (DSP), etc. The processing circuitry 810 may also include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an application-specific instruction set processor (ASIP), or the like.

[0086] The optical transmitter 820 may be any transmitter capable of converting binary data into PAM-4 optical signals and transmitting the symbols via an optical transmission medium 830. In certain examples, the optical transmitter 820 may also include optical receiver functionalities, in which case the optical transmitter 820 may be used to receive data from the memory device 850 in addition to sending data to the memory device 850. If the optical transmitter 820 does include receiving functionality, the receiving functionality may be provided by circuitry corresponding to that of the example optical receivers 100 described above.

[0087] The optical receiver 840 may include circuitry corresponding to that of the example optical receivers 100 described above. In certain examples, the optical receiver 840 may also include optical transmission functionalities, in which case the optical receiver 840 may be used to transmit data to the processing circuitry 810 in addition to receiving data from the processing circuitry 810.

[0088] The memory device 850 may be any non-transitory machine readable medium, which may include volatile storage media (e.g., DRAM, SRAM, etc.) and/or non-volatile storage media (e.g. , PROM, EPROM, EEPROM, NVRAM, hard drives, optical disks, etc.).

[0089] The optical receiver 100 may be used in any device that is to receive PAM-4 encoded optical signals. For example, the optical receiver 100 may be used in network devices, such as switches, routers, hubs, and the like. As another example, the optical receiver 100 could be used in high-speed rack-to-rack interconnects within a datacenter.

[0090] In the description above, the inputs and/or outputs of various components were described as having a logical high voltage or a logical low voltage and/or were described as being a logical 1 or a logical 0. This description is merely for convenience, and it will be understood that opposite logical relations could be used, with corresponding changes to the components to account for the changed logic.

[0091] The foregoing describes example optical receivers. While the above disclosure has been shown and described with reference to the foregoing examples, it should be understood that other forms, details, and

implementations may be made without departing from the spirit and scope of this disclosure.