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Pub. No.:    WO/2017/179908    International Application No.:    PCT/KR2017/003965
Publication Date: 19.10.2017 International Filing Date: 12.04.2017
H01L 33/02 (2010.01), H01L 33/10 (2010.01), H01L 33/46 (2010.01)
Applicants: LG INNOTEK CO., LTD. [KR/KR]; 98, Huam-ro Jung-gu Seoul 04637 (KR)
Inventors: PARK, Hyung Jo; (KR)
Agent: PARK, Young Bok; (KR).
HWANG, Young Wook; (KR)
Priority Data:
10-2016-0044566 12.04.2016 KR
(KO) 반도체 소자
Abstract: front page image
(EN)One embodiment provides a semiconductor device comprising: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; and a reflective layer disposed on the third semiconductor layer, wherein the part between the first and second semiconductor layers, the part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region, and the conductivity of the first semiconductor layer and the conductivity of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.
(FR)Selon un mode de réalisation, l'invention concerne un dispositif à semi-conducteur qui comporte : un substrat ; une première couche semi-conductrice disposée sur le substrat; une deuxième couche semi-conductrice disposée sur la première couche semi-conductrice ; une troisième couche semi-conductrice disposée sur la deuxième couche semi-conductrice ; une couche réfléchissante, disposée sur la troisième couche semi-conductrice, la partie située entre les première et deuxième couches semi-conductrices, la partie située entre les troisième et deuxième couches semi-conductrices et la deuxième couche semi-conductrice comportant une zone de déplétion, la conductivité de la première couche semi-conductrice et la conductivité de la troisième couche semi-conductrice étant différentes l'une de l'autre, et la deuxième couche semi-conductrice comportant une couche semi-conductrice intrinsèque.
(KO)실시예는 기판; 상기 기판 상에 배치되는 제1 반도체층; 상기 제1 반도체층 상에 배치되는 제2 반도체층; 상기 제2 반도체층 상에 배치되는 제3 반도체층; 및 상기 제3 반도체층 상에 배치되는 반사층을 포함하고, 상기 제1 및 제2 반도체층 사이, 상기 제3 및 제2 반도체층 사이 및 상기 제2 반도체층은 공핍 영역을 포함하고, 상기 제1 반도체층의 도전형과 상기 제3 반도체층의 도전형은 서로 다르고, 상기 제2 반도체층은 진성 반도체층을 포함하는 반도체 소자를 제공한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)