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1. (WO2017179448) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2017/179448 International Application No.: PCT/JP2017/013652
Publication Date: 19.10.2017 International Filing Date: 31.03.2017
IPC:
H01L 23/29 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
Applicants:
株式会社東海理化電機製作所 KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO [JP/JP]; 愛知県丹羽郡大口町豊田三丁目260番地 260, Toyota 3-chome, Ohguchi-cho, Niwa-gun, Aichi 4800195, JP
Inventors:
山口 英也 YAMAGUCHI, Hideya; JP
七田 健斗 SHICHITA, Kento; JP
Agent:
平田 忠雄 HIRATA, Tadao; JP
Priority Data:
2016-08113214.04.2016JP
2016-16266223.08.2016JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) A semiconductor device 1 has a substrate 2 covered with a sealing resin 70, and an electronic circuit 4 and a resist 3, which are formed on the substrate. The substrate 2 has: a forming section 30, on which the resist 3 is formed; a non-forming section 31 in contact with the sealing resin without having the resist 3 formed thereon; and a recessed section 5, the inside of which is filled with the resist 3 or the sealing resin 70, and to which stress received from the sealing resin is concentrated.
(FR) L'invention porte sur un dispositif à semi-conducteur (1) qui comprend un substrat (2) recouvert d'une résine d'étanchéité (70), et un circuit électronique (4) et un résist (3) qui sont formés sur le substrat. Le substrat (2) comprend : une section de formation (30), sur laquelle le résist est formé; une section de non-formation (31) en contact avec la résine d'étanchéité sans avoir le résist (3) formé sur elle; et une section évidée (5), dont l'intérieur est rempli du résist (3) ou de la résine d'étanchéité (70), et sur laquelle les contraintes reçues de la résine d'étanchéité sont concentrées.
(JA) 半導体装置1は、封止樹脂70によって覆われた基板2と、基板上に形成された電子回路4およびレジスト3を有し、基板2は、レジスト3が形成された形成部30と、レジスト3が形成されずに封止樹脂と接触する非形成部31と、内部にレジスト3又は封止樹脂70が充填され、封止樹脂から受ける応力が集中する凹部5とを有している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)