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1. (WO2017175480) SHEET FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT AND METHOD FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT

Pub. No.:    WO/2017/175480    International Application No.:    PCT/JP2017/005141
Publication Date: Fri Oct 13 01:59:59 CEST 2017 International Filing Date: Tue Feb 14 00:59:59 CET 2017
IPC: H01L 25/065
C09J 7/00
C09J 11/04
C09J 11/08
C09J 201/00
H01L 21/301
H01L 25/07
H01L 25/18
Applicants: LINTEC CORPORATION
リンテック株式会社
Inventors: NEZU Yusuke
根津 裕介
SUGINO Takashi
杉野 貴志
Title: SHEET FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT AND METHOD FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT
Abstract:
This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the material that constitutes the adhesive layer 13 has a pre-curing melt viscosity at 90 °C of 1.0×100-5.0×105 Pa·s, and the cured product has an average linear expansion coefficient at 0-130 °C of 45 ppm or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit in which connection resistance between the semiconductor chips does not easily change and which is highly reliable.