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1. (WO2017172322) METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT WITH A REQUESTED FEATURE SET
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Pub. No.: WO/2017/172322 International Application No.: PCT/US2017/021611
Publication Date: 05.10.2017 International Filing Date: 09.03.2017
IPC:
G06F 21/54 (2013.01) ,G06F 21/76 (2013.01) ,G06F 21/57 (2013.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50
Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
52
during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
54
by adding security routines or objects to programs
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70
Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71
to assure secure computing or processing of information
76
in application-specific integrated circuits [ASICs] or field-programmable devices, e.g. field-programmable gate arrays [FPGAs] or programmable logic devices [PLDs]
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50
Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
57
Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
MCLEAN, Ivan; US
MOSKOVICS, Stuart; US
CAMPBELL, Bryan; US
DRAGICEVICH, Mark; US
Agent:
FAWCETT, Robroy; US
Priority Data:
15/234,87911.08.2016US
62/314,92829.03.2016US
Title (EN) METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT WITH A REQUESTED FEATURE SET
(FR) PROCÉDÉ ET APPAREIL DE CONFIGURATION D’UN CIRCUIT INTÉGRÉ COMPORTANT UN ENSEMBLE D’ATTRIBUTS REQUIS
Abstract:
(EN) A method for configuring the features of an integrated circuit. In the method, the integrated circuit receives a feature vector message from a first party. The feature vector message is included in a response to a feature set request from the first party to a second party. The integrated circuit configures at least one feature of the integrated circuit based on a feature vector in the feature vector message. The integrated circuit generates an attestation result based on the at least one configured feature of the integrated circuit and using a key securely stored in the integrated circuit and known to the second party and not known to the first party. The integrated circuit forwards the attestation result to the first party.
(FR) L’invention concerne un procédé de configuration des attributs d’un circuit intégré. Selon le procédé, le circuit intégré reçoit un message de vecteur d’attributs d’une première partie. Le message de vecteur d’attributs est inclus dans une réponse à une requête d'ensemble d'attributs de la première partie à une deuxième partie. Le circuit intégré configure au moins un attribut du circuit intégré sur la base d’un vecteur d’attributs dans le message de vecteur d’attributs. Le circuit intégré génère un résultat d’attestation sur la base de l’attribut ou des attributs configurés du circuit intégré et au moyen d’une clé contenue de manière sécurisée dans le circuit intégré et connue de la deuxième partie et non connu de la première partie. Le circuit intégré transfère le résultat d’attestation à la première partie.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)