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1. (WO2017172285) MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL

Pub. No.:    WO/2017/172285    International Application No.:    PCT/US2017/021003
Publication Date: Fri Oct 06 01:59:59 CEST 2017 International Filing Date: Tue Mar 07 00:59:59 CET 2017
IPC: G06F 13/40
G06F 13/16
Applicants: INTEL CORPORATION
Inventors: VOGT, Pete
Title: MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL
Abstract:
A system with memory includes a repeater architecture where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second group of signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices. The second group of signal lines extends the memory channel to the second group of memory devices. The second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel.