Search International and National Patent Collections

1. (WO2017172255) PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTH

Pub. No.:    WO/2017/172255    International Application No.:    PCT/US2017/020573
Publication Date: Fri Oct 06 01:59:59 CEST 2017 International Filing Date: Sat Mar 04 00:59:59 CET 2017
IPC: G06F 9/30
Applicants: INTEL CORPORATION
Inventors: SHANBHOGUE, Vedvyas
ROBINSON, Stephen J.
BRYANT, Christopher D.
BRANDT, Jason W.
Title: PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTH
Abstract:
A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.