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1. (WO2017172244) POWER SIDE-CHANNEL ATTACK RESISTANT ADVANCED ENCRYPTION STANDARD ACCELERATOR PROCESSOR

Pub. No.:    WO/2017/172244    International Application No.:    PCT/US2017/020497
Publication Date: Fri Oct 06 01:59:59 CEST 2017 International Filing Date: Fri Mar 03 00:59:59 CET 2017
IPC: H04L 9/06
Applicants: INTEL CORPORATION
Inventors: KUMAR, Raghavan
MATHEW, Sanu K
SATPATHY, Sudhir K.
SURESH, Vikram B.
Title: POWER SIDE-CHANNEL ATTACK RESISTANT ADVANCED ENCRYPTION STANDARD ACCELERATOR PROCESSOR
Abstract:
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.