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1. (WO2017172221) N PLANE TO 2N PLANE INTERFACE IN A SOLID STATE DRIVE (SSD) ARCHITECTURE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/172221 International Application No.: PCT/US2017/020257
Publication Date: 05.10.2017 International Filing Date: 01.03.2017
IPC:
G06F 3/06 (2006.01) ,G06F 12/02 (2006.01) ,G11C 16/10 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
Applicants: INTEL CORPORATION[US/US]; Intel Corporation 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors: MADRASWALA, Aliasgar; US
GUO, Xin; US
JORGENSEN, Joel; US
Agent: ANDERSON, Vincent; US
NELSON, Kenneth; US
Priority Data:
15/087,07131.03.2016US
Title (EN) N PLANE TO 2N PLANE INTERFACE IN A SOLID STATE DRIVE (SSD) ARCHITECTURE
(FR) INTERFACE DE PLAN N À 2N DANS UNE ARCHITECTURE DE LECTEUR À SEMI-CONDUCTEURS (SSD)
Abstract:
(EN) A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.
(FR) Selon la présente invention, un lecteur à semi-conducteurs comprend un dispositif de commande muni d'une interface matérielle comportant moins de plans de cellules de mémoire que ceux qui sont compris dans la mémoire non volatile. Par exemple, une interface matérielle de dispositif de commande peut comprendre une interface de plan 1N couplée à un dispositif de mémoire non volatile comportant des plans 2N de cellules de mémoire. Pour des transactions d'accès aux données entre le dispositif de commande et le dispositif de mémoire non volatile, des première et seconde séquences de commande consécutives de plan 1N sont interprétées comme une séquence de commande de plan 2N unique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)