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1. (WO2017172173) INSTRUCTION, CIRCUITS, AND LOGIC FOR GRAPH ANALYTICS ACCELERATION
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Pub. No.: WO/2017/172173 International Application No.: PCT/US2017/019845
Publication Date: 05.10.2017 International Filing Date: 28.02.2017
IPC:
G06F 9/30 (2006.01) ,G06F 9/38 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
WU, Lisa K.; US
HAM, Tae Jun; US
SATISH, Nadathur Rajagopalan; US
SUNDARAM, Narayanan; US
Agent:
KOMENDA, J. Kyle; US
Priority Data:
15/089,23201.04.2016US
Title (EN) INSTRUCTION, CIRCUITS, AND LOGIC FOR GRAPH ANALYTICS ACCELERATION
(FR) INSTRUCTION, CIRCUITS ET LOGIQUE POUR L'ACCÉLÉRATION D'ANALYSE DE GRAPHE
Abstract:
(EN) A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.
(FR) Selon l'invention, un processeur comprend une partie frontale contenant de la circuiterie permettant de recevoir et de décoder une instruction. L'instruction doit effectuer une fonction d'analyse de graphe et transmettre l'instruction à un accélérateur de graphe. L'accélérateur de graphe comprend de la circuiterie servant à traiter des sommets de graphe et des arêtes de graphe en tant que types de données, exécuter l'instruction, et transmettre les résultats de l'instruction à un sous-système de mémoire du processeur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)