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1. WO2017172122 - AUXILIARY CACHE FOR REDUCING INSTRUCTION FETCH AND DECODE BANDWIDTH REQUIREMENTS

Publication Number WO/2017/172122
Publication Date 05.10.2017
International Application No. PCT/US2017/018923
International Filing Date 22.02.2017
IPC
G06F 12/0802 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 12/0875
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0875with dedicated cache, e.g. instruction or stack
G06F 2212/452
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
45Caching of specific data in cache memory
452Instruction code
G06F 9/30145
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
G06F 9/30167
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
3016Decoding the operand specifier, e.g. specifier format
30167of immediate specifier, e.g. constants
G06F 9/3017
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
3017Runtime instruction translation, e.g. macros
G06F 9/30181
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • AGRON, Jason M.
  • MERRICK, Alex
  • MEKKAT, Vineeth
Agents
  • KOMENDA, J. Kyle
Priority Data
15/087,78631.03.2016US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) AUXILIARY CACHE FOR REDUCING INSTRUCTION FETCH AND DECODE BANDWIDTH REQUIREMENTS
(FR) MÉMOIRE CACHE AUXILIAIRE POUR RÉDUIRE LES EXIGENCES DE BANDE PASSANTE D'EXTRACTION ET DE DÉCODAGE D'INSTRUCTION
Abstract
(EN)
A hardware-software co-designed processor includes a front end to decode an instruction, an execution unit to execute the instruction, an auxiliary cache to store auxiliary information for consumption during execution of the instruction, an instruction blender, and a retirement unit to retire the instruction. The auxiliary information may include long immediate values, non-working instructions for emulating an untranslated instruction stream, or execution hints, and is not decoded by the front end. The auxiliary cache includes circuitry to receive the auxiliary information from a binary translator, to store the auxiliary information in the auxiliary cache, and to provide the auxiliary information to the instruction blender prior to execution. The instruction blender includes circuitry to receive the auxiliary information, to blend the instruction with the auxiliary information, and to provide the blended instruction to the execution unit. Use of the auxiliary cache may reduce fetch and decode bandwidth requirements.
(FR)
Selon l'invention, un processeur co-conçu matériel-logiciel comprend un logiciel frontal pour décoder une instruction, une unité d'exécution pour exécuter l'instruction, une mémoire cache auxiliaire pour stocker des informations auxiliaires pour une consommation durant l'exécution de l'instruction, un dispositif de mélange d'instructions, et une unité de retrait pour retirer l'instruction. Les informations auxiliaires peuvent comprendre de longues valeurs intermédiaires, des instructions non de fonctionnement pour émuler un flux d'instructions non traduit, ou des commentaires d'aide d'exécution, et ne sont pas décodées par le logiciel frontal. La mémoire cache auxiliaire comprend une circuiterie pour recevoir les informations auxiliaires à partir d'un traducteur binaire, pour stocker les informations auxiliaires dans la mémoire cache auxiliaire, et pour fournir les informations auxiliaires au dispositif de mélange d'instructions avant l'exécution. Le dispositif de mélange d'instructions comprend une circuiterie pour recevoir les informations auxiliaires, pour mélanger l'instruction avec les informations auxiliaires, et pour fournir l'instruction mélangée à l'unité d'exécution. L'utilisation de la mémoire cache auxiliaire peut réduire les exigences de bande passante d'extraction et de décodage.
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