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1. WO2017172010 - LEADFRAME TOP-HAT MULTI-CHIP SOLUTION

Publication Number WO/2017/172010
Publication Date 05.10.2017
International Application No. PCT/US2017/015399
International Filing Date 27.01.2017
IPC
H01L 23/495 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
495Lead-frames
H01L 23/482 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
CPC
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
H01L 2224/73265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73251on different surfaces
73265Layer and wire connectors
H01L 23/49513
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49503characterised by the die pad
49513having bonding material between chip and die pad
H01L 23/4952
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49517Additional leads
4952the additional leads being a bump or a wire
H01L 23/49548
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49541Geometry of the lead-frame
49548Cross section geometry
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • VREMAN, Gerrit J.
Agents
  • PFLEGER, Edmund P.
Priority Data
15/089,24401.04.2016US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LEADFRAME TOP-HAT MULTI-CHIP SOLUTION
(FR) SOLUTION MULTIPUCE À CHAPEAU SUPÉRIEUR DE GRILLE DE CONNEXION
Abstract
(EN)
A semiconductor package may include an electrically conductive leadframe having a aperture extending from an upper surface of the leadframe to the lower surface of the leadframe. A wirebond die may be attached or affixed to the upper surface of the leadframe in a location that at least partially obstructs the aperture. A flip-chip die may be disposed proximate the bottom surface of the leadframe at least partially in the aperture. The flip-chip die may be physically coupled to the wirebond die, the leadframe, or both. A mold compound that exposes the lands on the leadframe and the solder bumps or balls on the flip-chip die may at least partially encapsulate the semiconductor package.
(FR)
L'invention concerne un boîtier de semiconducteur qui peut comprendre une grille de connexion électriquement conductrice ayant une ouverture qui s'étend depuis une surface supérieure de la grille de connexion jusqu'à la surface inférieure de la grille de connexion. Une matrice de connexion par fil peut être attachée ou fixée à la surface supérieure de la grille de connexion à un emplacement qui obstrue au moins partiellement l'ouverture. Une matrice à puce retournée peut être disposée à proximité de la surface inférieure de la grille de connexion au moins partiellement dans l'ouverture. La matrice à puce retournée peut être physiquement couplée à la matrice de connexion par fil, à la grille de connexion, ou aux deux. Un composé de moulage qui expose les pastilles sur la grille de connexion et les bosses ou les billes de soudure sur la matrice à puce retournée peut au moins partiellement encapsuler le boîtier de semiconducteur.
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